uPI Semiconductor Corp., http://www.upi-semi.com

Rev. F03, File Name: uP6281-DS-F0300

uP6281

8

Application Information

The power dissipation in uP6281 is dependent of the supply

voltage, the PWM frequency and the input capacitance of

the MOSFET:

}

f]

C

V

)

C

C

(

V

[

I{

V

P

PWM

U

_

OSS

IN

L

_

ISS

U

_

ISS

CC

CC

CC

LOSS

×

+

+

+

=

where V

CC is the supply voltage, ICC is the operation current

of the control circuit, C

ISS_U and CISS_L are the total input

capacitance of the upper and lower MOSFET respectively,

V

IN is the supply voltage of the buck converter, COSS_U is the

reverse transfer capacitance regarding the Miller effect and

f

PWM is the PWM input frequency. Take a typical case for

example, V

CC = 12V, ICC = 1mA, CISS_U = 2x1.5nF, COSS_U =

2x0.1nF, V

IN = 12V, CISS_L = 2x3nF, fOSC = 300kHz, the

power dissipation is calculated as:

W

41

.

0

}

kHz

300

]

nF

2

.

0

V

12

)

nF

6

nF

3

(

V

12

[

mA

1

{

V

12

PLOSS

=

×

+

+

+

=

The uP6281 is available in thermal enhanced PSOP-8L or

WDFN3x3-8L packages. However, the thermal resistance

θ

JA still highly depends on the PCB design. Copper plane

under the exposed pad is an effective heatsink and is useful

for improving thermal conductivity. Figure 1 shows the

relationship between thermal resistance

θ

JA of PSOP-8L

package vs. copper area on a standard JEDEC 51-7 (4

layers, 2S2P) thermal test board at T

A = 25

O

C. A 50mm2

copper plane reduces

θ

JA from 75

O

C/W to 50OC/W.

60

70

50

40

30

20

10

0

60

70

50

40

30

90

100

80

Copper Area (mm2)

Figure 1. Thermal Resistance

θ

JA vs. Copper Area

Take the above case for example, 0.41W power loss will

cause 0.41W x 50OC/W = 20.5OC temperature raise with

50mm2 copper area.