AM29BDS128HD8 datasheet(13/89 Pages) SPANSION

13 / 89 page

May 10, 2006 27024B3

Am29BDS128H/Am29BDS640H

D A TA

SH EE T

DEVICE BUS OPERATIONS

This section describes the requirements and use of the

device bus operations, which are initiated through the

internal command register. The command register

itself does not occupy any addressable memory loca-

tion. The register is composed of latches that store the

commands, along with the address and data informa-

tion needed to execute the command. The contents of

the register serve as inputs to the internal state

machine. The state machine outputs dictate the func-

tion of the device. Table 1 lists the device bus opera-

tions, the inputs and control levels they require, and the

resulting output. The following subsections describe

each of these operations in further detail.

Table 1.

Device Bus Operations

Legend: L = Logic 0, H = Logic 1, X = Don’t Care, S = Stable Logic 0 or 1 but no transitions.

Note: Default active edge of CLK is the rising edge.

Requirements for Asynchronous Read

Operation (Non-Burst)

To read data from the memory array, the system must

first assert a valid address on Amax–A0, while driving

AVD# and CE# to VIL. WE# should remain at VIH. The

rising edge of AVD# latches the address. The data will

appear on DQ15–DQ0. Since the memory array is

divided into four banks, each bank remains enabled for

read access until the command register contents are

altered.

Address access time (tACC) is equal to the delay from

stable addresses to valid output data. The chip enable

access time (tCE) is the delay from the stable

addresses and stable CE# to valid data at the outputs.

The output enable access time (tOE) is the delay from

the falling edge of OE# to valid data at the output.

The internal state machine is set for reading array data

in asynchronous mode upon device power-up, or after

a hardware reset. This ensures that no spurious alter-

ation of the memory content occurs during the power

transition.

Requirements for Synchronous (Burst)

Read Operation

The device is capable of continuous sequential burst

operation and linear burst operation of a preset length.

When the device first powers up, it is enabled for asyn-

chronous read operation.

Prior to entering burst mode, the system should deter-

mine how many wait states are desired for the initial

word (tIACC) of each burst access, what mode of burst

operation is desired, which edge of the clock will be the

Operation

CE#

OE#

WE#

Amax–0

DQ15–0

RESET#

CLK

(See

Note)

AVD#

Asynchronous Read - Addresses Latched

Addr In

I/O

Asynchronous Read - Addresses Steady State

Addr In

I/O

Asynchronous Write

Addr In

I/O

Synchronous Write

Addr In

I/O

Standby (CE#)

HIGH Z

Hardware Reset

HIGH Z

Burst Read Operations

Load Starting Burst Address

Addr In

Advance Burst to next address with

appropriate Data presented on the Data Bus

HIGH Z

Burst

Data Out

Terminate current Burst read cycle

HIGH Z

Terminate current Burst read cycle via

RESET#

HIGH Z

Terminate current Burst read cycle and start

new Burst read cycle

HIGH Z

I/O

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