AM29BDS128H datasheet(49/89 Pages) SPANSION

49 / 89 page

May 10, 2006 27024B3

Am29BDS128H/Am29BDS640H

D A TA

SH EE T

Table 21.

Sector Protection Command Definitions

Legend:

X = Don’t care

PA = Address of the memory location to be programmed. Addresses latch

on the rising edge of the AVD# pulse or active edge of CLK which ever

comes first.

SA = Address of the sector to be verified (in autoselect mode) or erased.

Address bits Amax–A12 uniquely select any sector.

BA = Address of the bank (BDS128H: A22–A20; BDS640H: A21–A19) for

which command is being written.

SLA = Address of the sector to be locked. Set sector address (SA) and

either A6 = 1 for unlocked or A6 = 0 for locked.

OW = Address (A7–A0) is (00011010).

PD3–PD0 = Password Data. PD3–PD0 present four 16 bit combinations

that represent the 64-bit password.

PWA = Password Address. Address bits A1 and A0 are used to select

each 16-bit portion of the 64-bit entity.

PL = Address (A7–A0) is (00001010)

RD(0) = DQ0 protection indicator bit. If protected, DQ0 = 1.

If unprotected, DQ0 = 0.

RD(1) = DQ1 protection indicator bit. If protected, DQ1 = 1.

If unprotected, DQ1 = 0.

SBA = Sector address block to be protected.

SL = Address (A7–A0) is (00010010)

WD= Write Data. See “Configuration Register” definition for specific write

data

WP = Address (A7–A0) is (00000010)

WPE = Address (A7–A0) is (01000010)

Notes:

See Table 1 for description of bus operations.

All values are in hexadecimal.

Shaded cells indicate read cycles. All others are write cycles.

Data bits DQ15–DQ8 are don’t care in command sequences, except

for RD, PD, WD, PWD, and PD3–PD0.

Unless otherwise noted, address bits Amax–A12 are don’t cares.

Writing incorrect address and data values or writing them in the

improper sequence may place the device in an unknown state. The

system must write the reset command to return the device to

reading array data.

No unlock or command cycles required when bank is reading array

data.

Not supported in Synchronous Read Mode, command mode verify

are always asynchronous read operations.

The fourth cycle programs the addressed locking bit. The fifth and

sixth cycles are used to validate whether the bit has been fully

programmed. If DQ0 (in the sixth cycle) reads 0, the program

command must be issued and verified again.

10. The fourth cycle erases all PPBs. The fifth and sixth cycles are used

to validate whether the bits have been fully erased. If DQ0 (in the

sixth cycle) reads 1, the erase command must be issued and verified

again.

11. The entire four bus-cycle sequence must be entered for each portion

of the password.

12. Before issuing the erase command, all PPBs should be programmed

in order to prevent over-erasure of PPBs.

13. In the fourth cycle, 01h indicates PPB set; 00h indicates PPB not

set.

Command Sequence

(Notes)

Bus Cycles (Notes 1–6)

First

Second

Third

Fourth

Fifth

Sixth

Seventh

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Entry

555

2AA

555

Exit

555

2AA

555

Protection Bit

Program (8, 9)

555

2AA

555

SA+OW

RD(0)

Program (11)

555

2AA

555

XX[0–3]

PD[0–3]

Verify (11)

555

2AA

555

XX[0–3]

PD[0–3]

Unlock (11)

555

2AA

555

XX0

PD0

XX1

PD1

XX2

PD2

XX3

PD3

Program (8, 9)

555

2AA

555

SBA+WP

RD(0)

All Erase

(8, 10, 12)

555

2AA

555

WPE

SBA+

WPE

RD(0)

Status (13)

555

2AA

BA+555

SBA+WP

RD(0)

Set

555

2AA

555

Status (8)

555

2AA

BA+555

RD(1)

Write

555

2AA

555

Erase

555

2AA

555

Status

555

2AA

BA+555

RD(0)

Locking Bit Program

(8, 9)

555

2AA

555

RD(0)

Locking Bit Program

(8, 9)

555

2AA

555

RD(0)

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