AM29BDS128H datasheet(35/89 Pages) SPANSION

35 / 89 page

May 10, 2006 27024B3

Am29BDS128H/Am29BDS640H

D A TA

SH EE T

COMMAND DEFINITIONS

Writing specific address and data commands or

sequences into the command register initiates device

operations. Table 20, “Memory Array Command Defini-

tions,” on page 46 defines the valid register command

sequences. Writing incorrect address and data values

or writing them in the improper sequence may place the

device in an unknown state. The system must write the

reset command to return the device to reading array

data. Refer to the AC Characteristics section for timing

diagrams.

Reading Array Data

The device is automatically set to reading array data

after device power-up. No commands are required to

retrieve data in asynchronous mode. Each bank is

ready to read array data after completing an Embedded

Program or Embedded Erase algorithm.

After the device accepts an Erase Suspend command,

the corresponding bank enters the erase-sus-

pend-read mode, after which the system can read data

from any non-erase-suspended sector within the same

bank. After completing a programming operation in the

Erase Suspend mode, the system may once again

read array data from any non-erase-suspended sector

within the same bank. See the “Erase Suspend/Erase

Resume Commands” section on page 39 for more

information.

The system must issue the reset command to return a

bank to the read (or erase-suspend-read) mode if DQ5

goes high during an active program or erase operation,

or if the bank is in the autoselect mode. See the “Reset

Command” section on page 36 for more information.

See also “Requirements for Asynchronous Read Oper-

ation (Non-Burst)” section on page 11 and “Require-

ments for Synchronous (Burst) Read Operation”

section on page 11 for more information. The Asyn-

chronous Read and Synchronous/Burst Read tables

provide the read parameters, and Figure 16, “CLK Syn-

chronous Burst Mode Read (rising active CLK),” on

page 58, Figure 18, “Synchronous Burst Mode Read,”

on page 59, and Figure 31, “Asynchronous Mode Read

with Latched Addresses,” on page 67 show the timings.

Set Configuration Register Command Se-

quence

The device uses a configuration register to set the

various burst parameters: number of wait states, burst

read mode, active clock edge, RDY configuration, and

synchronous mode active. The configuration register

must be set before the device will enter burst mode.

The configuration register is loaded with a three-cycle

command sequence. The first two cycles are standard

unlock sequences. On the third cycle, the data should

be C0h, address bits A11–A0 should be 555h, and

address bits A19–A12 set the code to be latched. The

device will power up or after a hardware reset with the

default setting, which is in asynchronous mode. The

chronous mode. The configuration register can not be

changed during device operations (program, erase, or

sector lock).

Figure 3.

Synchronous/Asynchronous State

Diagram

Read Mode Setting

On power-up or hardware reset, the device is set to be

in asynchronous read mode. This setting allows the

system to enable or disable burst mode during system

operations. Address A19 determines this setting: “1” for

asynchronous mode, “0” for synchronous mode.

Programmable Wait State Configuration

The programmable wait state feature informs the

device of the number of clock cycles that must elapse

after AVD# is driven active before data will be available.

This value is determined by the input frequency of the

device. Address bits A14–A12 determine the setting

(see Table 14, “Programmable Wait State Settings,” on

page 34).

The wait state command sequence instructs the device

to set a particular number of clock cycles for the initial

access in burst mode. The number of wait states that

should be programmed into the device is directly

related to the clock frequency.

Power-up/

Hardware Reset

Asynchronous Read

Mode Only

Synchronous Read

Mode Only

Set Burst Mode

Configuration Register

Command for

Synchronous Mode

(D15 = 0)

Set Burst Mode

Configuration Register

Command for

Asynchronous Mode

(D15 = 1)

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