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R2000 датащи(PDF) 42 Page - List of Unclassifed Manufacturers |
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R2000 датащи(HTML) 42 Page - List of Unclassifed Manufacturers |
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42 / 75 page ![]() Indy® R2000 Electrical, Mechanical, & Thermal Specification Revision 2.0, Copyright © 2015, Impinj, Inc. 42 Addr. Name R/W Bit Description Reset Type Comment 109 AUTO_READ R/W 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Auto-read of soft demod data Auto-read of phase rotation angle Auto-read of pream_mag Auto-read of rcorr_mag Auto-read WB rssi_rt_values Auto-read NB rssi_rt_values Auto-read of rssi_blk_rt_log Auto-read of rssi_blk_rt_lin Auto-read of rx_dec_q Auto-read of rx_dec_i Auto-read of rx_filt_q Auto-read of rx_filt_i Auto-read of rx_ph Auto-read of ISR Auto-read of RX FIFO h0000 Serial interface control Register h29C Register h276 Register h2D6 Register h2BC Register h287 Register h286 Register h288 Register h28A Register h214 Register h212 Register h263 Register h261 Register h273 Register h107 Register h105 10a DIS_T2R R/W 3 2 1 0 Select frame format Enable low overhead frame Disable T2R_D2 Disable T2R_D1 h0000 Serial interface control. Select frame format: 1 = Two data words per frame. 0 = Four data words per frame. Observe that T2R_D2 must not be enabled when T2R_D1 is disabled. 10b SEED_HIGH R/W 15:0 LFSR seed high word hA5A5 10c SEED_LOW R/W 15:0 LFSR seed low word h5A5A 10D AUTO_READ_DEC R/W 15:8 7:0 Decimation of block averaged RSSI Decimation of RX data path auto read h0000 The down-sampling factor is the register value+1. No filtering is performed, i.e., the effect of folding must be kept in mind. 10e CLKOUT_CTRL R/W 3:0 Clock output setting h0005 The clock output setting is decoded as follows: 0 = 48 MHz 1 = 24 MHz 2 = 12 MHz 3 = 6 MHz 4 = 3 MHz 5 = 1.5 MHz (default) 6 = Constant low output 7 = Constant high output 10F AUTO_READ_DEC _RSSI R/W 15:8 7:0 Decimation of WB RSSI auto-read Decimation of NB RSSI auto- read h0000 Auto-read decimation for RSSI registers. The down-sampling factor is the register value+1. No filtering is performed, i.e., the effect of folding must be kept in mind. 110 LOCK_DET_ THOLD R/W 7:0 PLL up/down pulse width threshold h0000 The threshold for the high period of the up/down signal when the PLL is deemed unlocked. Specified in 48 MHz clock cycles. |
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