R2000 datasheet(41/75 Pages) ETC

41 / 75 page

Indy® R2000 Electrical, Mechanical, & Thermal Specification

Addr.

Name

R/W

Bit

Description

Reset

Type

Comment

106

DP_STAT

7:4

3:0

RX FIFO status

TX FIFO status

h0000

Both the RX and the TX

FIFO has 16 positions.

The RX FIFO status is the

number of free positions in

the FIFO. Zero value of the

status means both full

FIFO and one position

empty.

The TX FIFO status is the

number of occupied

positions in the FIFO. The

value hF means both full

FIFO and one position

empty.

DP_CTRL

6:4

2:0

Flush RX FIFO

RX FIFO watermark

Flush TX FIFO

TX FIFO watermark

h0044

The RX watermark is for

overflow while the TX

watermark is for underflow.

The watermark is indicated

through an interrupt. For

the RX FIFO the interrupt

is only asserted on writes

to the FIFO and for the TX

FIFO the interrupt is only

asserted of reads.

The watermarks are set to

4 by default.

Writing the flush bit only

clears the FIFO once.

107

ISR

SJC algorithm done

Filter tuning done

IF Filter too low

IF Filter too high

Lock detect change

IF LNA too low

IF LNA too high

Non-empty RX FIFO

AUX ADC done

SDI RX FIFO overflow

RX FIFO at watermark

RX time-out

RSSI done

ADC input overdriven

Read from TX FIFO

TX FIFO at watermark

h0000

Read clears all nibbles of

the interrupt register. Bits

15:12 are only readable

and cleared through the

indirect register map.

This register is auto-

readable.

The TX and RX watermark

interrupts occurs only

when the number of

entries in the FIFO is

exactly at the offset

specified by the

watermark.

Four more interrupts are

available through the

indirect memory. There are

only cleared when the

indirect memory is read.

108

DP_CTRL

R/W

7:0

Indirect address for

DP_CTRL

h0044

FIFO Watermark

programming.

See direct register map for

details.

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