÷4/÷5 Differential-to-3.3V LVPECL

Clock Generator

87354

DATASHEET

87354 REVISION A 2/12/15

1

©2015 Integrated Device Technology, Inc.

GENERAL DESCRIPTION

The

87354

is

a

high

perf or mance

÷4/÷5

Differential-to-3.3V LVPECL Clock Generator.The CLK, nCLK pair can ac-

cept most standard differential input levels.The 87354 is characterized to

operate from a 3.3V power supply.Guaranteed output and part-to-part skew

char acter istics mak e the 87354 ideal for those cloc k

distr ib ution

applications

demanding

w ell

defined

performance and repeatability.

FEATURES

• One differential 3.3V LVPECL output

• One CLK, nCLK input pair

• CLK, nCLK pair can accept the following differential

input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL

• Maximum clock input frequency: 1GHz

• Translates any single ended input signal (LVCMOS, LVTTL,

GTL) to LVPECL levels with resistor bias on nCLK input

• Part-to-part skew: 300ps (maximum)

• Propagation delay: 2.1ns (maximum)

• LVPECL mode operating voltage supply range:

V

CC = 3.0V to 3.465V, VEE = 0V

• -40°C to 85°C ambient operating temperature

• Available in lead-free RoHS compliant package

BLOCK DIAGRAM

PIN ASSIGNMENT

87354

8-Lead SOIC

3.90mm x 4.90mm x 1.37mm package body

M Package

Top View

CLK

nCLK

MR

F_SEL

1

2

3

4

Vcc

Q

nQ

VEE

8

7

6

5

Q

nQ

CLK

nCLK

÷4

MR

÷5

R

0

1

F_SEL