ICS1524A

16

PECL Outputs

For information on using the ICS1524A’s PECL output pins, please refer to Application Note 4: Designing a Custom

PECL Interface for the ICS1523

SSTL_3 Outputs

Unterminated Outputs

In the ICS1524A, unterminated SSTL_3 output pins display exponential transitions similar to those of rectangular

pulses presented to RC loads. The 10-90% rise time is typically 1.6 ns, and the corresponding fall time is typically

700 ps. In turn, this asymmetry contributes to duty cycle asymmetry at higher output frequencies. In the absence of

significant load capacitance (which can further increase rise and fall time), this asymmetry is the dominant factor

determining high-frequency performance of these single-ended outputs. Typically, no termination is required either for

the LOCK/REF, FUNC, and CLK/2 outputs or for CLK outputs up to approximately 135 MHz.

Terminated Outputs

SSTL_3 outputs are intended to terminate in low impedances to reduce the effect of external circuit capacitance.

Use of transmission line techniques enables use of longer traces between source and driver without increasing

ringing due to reflections. Where external capacitance is minimal and substantial voltage swing is required to meet

LVTTL VIH and VOL requirements, the intrinsic rise and fall times of ICS1524A SSTL outputs are only slightly improved

by termination in a low impedance.

The ICS1524A SSTL output source impedance is typically less than 60 Ohms. Termination impedance of 100 Ohms

reduces output swing by less than 30% which is more than enough to drive a single load of LVTTL inputs.

For more information on using the ICS1524A’s SSTL output pins, please refer to Application Note 3: Using SSTL_3

Outputs with CMOS or LVTTL Inputs

ICS1524A

VDD

SSTL-3 Output

330

Ω

150

Ω

Single

LVTTL

Load