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ICS1524AMLF датащи(PDF) 11 Page - Renesas Technology Corp

номер детали ICS1524AMLF
подробное описание детали  Dual Output Phase Controlled SSTL_3/PECL Clock Generator
PDF  25 Pages
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производитель  RENESAS [Renesas Technology Corp]
домашняя страница  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

ICS1524AMLF датащи(HTML) 11 Page - Renesas Technology Corp

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ICS1524A
ICS1524A Rev F 05/13/10
Name:
Oscillator Divider Register
Register:
7h
Index:
Read / Write
Bit Name
Bit #
Reset Value
Description
Osc_Div 0-6
0-6
0
Osc Divider Modulus
In_Sel
7
1
Input Select
Bit
Name
Description
0 - 6
Osc_Div 0-6
Oscillator Divider Modulus.
Divides the input from OSC (pin 12) by the set modulus.
The modulus equals the programmed value, plus 2.
Therefore, the modulus range is from 3 to 129.
7
In_Sel
Input Select — Selects the input to the Phase/Frequency Detector
0 = HSYNC
1 = Osc Divider
Name:
RESET Register
Register:
8 h
Index:
Write
Bit Name
Bit #
Reset Value
Description
DPA Reset
0 -3
x
Writing xAh to this register resets DPA working register 5
PLL Reset
4 -7
x
Writing 5xh to this register resets PLL working registers 1-3
Bit
Name
Description
0 - 3
DPA
Writing xAh to this register resets DPA working register 5
4 -7
PLL
Writing 5xh to this register resets PLL working registers 1-3
e
u
l
a
Vs
t
e
s
e
R
A
xA
P
D
x
5L
L
P
A
5L
L
P
d
n
a
A
P
D



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