AM29LV320D datasheet(13/55 Pages) SPANSION

13 / 55 page

November 15, 2004

Am29LV320D

Automatic Sleep Mode

The automatic sleep mode minimizes Flash de-

vice energy consumption. The device automati-

cally enables this mode when addresses remain

stable for tACC + 30 ns. The automatic sleep

mode is independent of the CE#, WE#, and

OE# control signals. Standard address access

timings provide new data when addresses are

changed. While in sleep mode, output data is

latched and always available to the system. ICC4

in the “DC Characteristics” on page 35 table

represents the automatic sleep mode current

specification.

RESET#: Hardware Reset Pin

The RESET# pin provides a hardware method

of resetting the device to reading array data.

When the RESET# pin is driven low for at least

a period of tRP, the device immediately termi-

nates any operation in progress, tristates all

output pins, and ignores all read/write com-

mands for the duration of the RESET# pulse.

The device also resets the internal state ma-

chine to reading array data. The operation that

was interrupted should be reinitiated once the

device is ready to accept another command se-

quence, to ensure data integrity.

Current is reduced for the duration of the RE-

SET# pulse. When RESET# is held at VSS±0.3

V, the device draws CMOS standby current

(ICC4). If RESET# is held at VIL but not within

VSS±0.3 V, the standby current is greater.

The RESET# pin may be tied to the system

reset circuitry. A system reset would thus also

reset the Flash memory, enabling the system to

read the boot-up firmware from the Flash

memory.

If RESET# is asserted during a program or

erase operation, the RY/BY# pin remains a “0”

(busy) until the internal reset operation is com-

plete, which requires a time of tREADY (during

Embedded Algorithms). The system can thus

monitor RY/BY# to determine whether the

reset operation is complete. If RESET# is as-

serted when a program or erase operation is

not executing (RY/BY# pin is “1”), the reset op-

eration is completed within a time of tREADY (not

during Embedded Algorithms). The system can

read data tRH after the RESET# pin returns to

VIH.

Refer to the AC Characteristics tables for RE-

SET# parameters and to Figure 15, on page 39

for the timing diagram.

Output Disable Mode

When the OE# input is at VIH, output from the

device is disabled. The output pins are placed in

the high impedance state.

Table 2. Top Boot Sector Addresses (Am29LV320DT) (Sheet 1 of 2)

Sector

Sector Address

A20–A12

Sector Size

(Kbytes/Kwords)

(x8)

Address Range

(x16)

Address Range

SA0

000000xxx

64/32

000000h–00FFFFh

000000h–07FFFh

SA1

000001xxx

64/32

010000h–01FFFFh

008000h–0FFFFh

SA2

000010xxx

64/32

020000h–02FFFFh

010000h–17FFFh

SA3

000011xxx

64/32

030000h–03FFFFh

018000h–01FFFFh

SA4

000100xxx

64/32

040000h–04FFFFh

020000h–027FFFh

SA5

000101xxx

64/32

050000h–05FFFFh

028000h–02FFFFh

SA6

000110xxx

64/32

060000h–06FFFFh

030000h–037FFFh

SA7

000111xxx

64/32

070000h–07FFFFh

038000h–03FFFFh

SA8

001000xxx

64/32

080000h–08FFFFh

040000h–047FFFh

SA9

001001xxx

64/32

090000h–09FFFFh

048000h–04FFFFh

SA10

001010xxx

64/32

0A0000h–0AFFFFh

050000h–057FFFh

SA11

001011xxx

64/32

0B0000h–0BFFFFh

058000h–05FFFFh

SA12

001100xxx

64/32

0C0000h–0CFFFFh

060000h–067FFFh

SA13

001101xxx

64/32

0D0000h–0DFFFFh

068000h–06FFFFh

SA14

001110xxx

64/32

0E0000h–0EFFFFh

070000h–077FFFh

SA15

001111xxx

64/32

0F0000h–0FFFFFh

078000h–07FFFFh

SA16

010000xxx

64/32

100000h–10FFFFh

080000h–087FFFh

SA17

010001xxx

64/32

110000h–11FFFFh

088000h–08FFFFh

SA18

010010xxx

64/32

120000h–12FFFFh

090000h–097FFFh

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