ICS548-05

T1/E1 CLOCK MULTIPLIER

CLOCK SYNTHESIZER

IDT® T1/E1 CLOCK MULTIPLIER

2

ICS548-05

REV D 091511

Pin Assignment

Output Clock Selection Table

Power Down Clock Selection Table

Key: 0 = connect directly to GND; 1 = connect directly to

VDD

Pin Descriptions

Key: XI, XO = crystal connections; the in put pin MSEL must be tied directly to VDD or GND.

For a clock input, connect the input X1 and leave X2 unconnected (floating).

12

1

11

2

10

X1/ICLK

X2

3

9

VDD

4

VDD

DC

5

REFEN

6

REFOUT

7

GND

8

GND

MSEL

GND

PDCLK

GND

DC

VDD

CLK

16

15

14

13

16-pin TSSOP

MSEL

Input (MHz)

CLK (MHz)

Pin 13

PIns 1, (16)

PIn 9

0

1.544

24.704

1

1.544

37.056

0

2.048

32.768

1

2.048

49.152

REFEN PDCLK

Power Down Selection Mode

Pin 4

PIn 11

0

0

The entire chip is off.

0

1

PLL and clock output run, REFOUT low.

1

0

REFOUT running, PLL off, CLK low.

1

1

All running.

Pin

Number

Pin

Name

Pin

Type

Pin Description

1

X1/ICLK

XI

Crystal connection. Connect this pin to a crystal or clock input.

2, 3, 8

VDD

Power

Connect to +3.3 V or +5 V. All VDD’s must be the same.

4

REFEN

Input

Reference Clock Enable. See table above. Connect to GND for best jitter/phase

noise.

5, 6, 7, 12

GND

Power

Connect to ground.

9

CLK

Output

Clock output set by input status of MSEL. See table above.

10, 15

DC

—

Don’t Connect. Do not connect these pins to anything.

11

PDCLK

Input

Power down clock. See table above.

13

MSEL

Input

Multiplier select pin. Selects x16 when low, x24 when high.

14

REFOUT

Output

Buffered reference output clock. Controlled by REFEN.

16

X2

XO

Crystal connection. Connect this pin to a crystal or leave unconnected for a clock.