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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ST72361 датащи(PDF) 35 Page - STMicroelectronics |
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ST72361 датащи(HTML) 35 Page - STMicroelectronics |
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35 / 224 page  ST72361 35/224 INTERRUPTS (Cont’d) 7.6 EXTERNAL INTERRUPTS 7.6.1 I/O Port Interrupt Sensitivity The external interrupt sensitivity is controlled by the ISxx bits in the EICR register (Figure 21). This control allows up to four fully independent external interrupt source sensitivities. Each external interrupt source can be generated on four (or five) different events on the pin: ■ Falling edge ■ Rising edge ■ Falling and rising edge ■ Falling edge and low level To guarantee correct functionality, the sensitivity bits in the EICR register can be modified only when the I1 and I0 bits of the CC register are both set to 1 (level 3). This means that interrupts must be disabled before changing sensitivity. The pending interrupts are cleared by writing a dif- ferent value in the ISx[1:0] of the EICR. Figure 21. External Interrupt Control Bits IS10 IS11 EICR SENSITIVITY CONTROL PBOR.0 PBDDR.0 PB0 ei1 INTERRUPT SOURCE PORT B [5:0] INTERRUPTS PB0 PB1 PB2 PB3 IS20 IS21 EICR SENSITIVITY CONTROL PCOR.7 PCDDR.7 PC1 ei2 INTERRUPT SOURCE PORT C [2:1] INTERRUPTS PC1 PC2 IS00 IS01 EICR SENSITIVITY CONTROL PAOR.0 PADDR.0 PA0 ei0 INTERRUPT SOURCE PORT A [7:0] INTERRUPTS PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 / AWUPR AWUFH Oscillator To Timer Input Capture 1 PB4 PB5 IS30 IS31 EICR SENSITIVITY CONTROL PDOR.0 PDDDR.0 PD0 ei3 INTERRUPT SOURCE PORT D [7:6, 4, 1:0] INTERRUPTS PD0 PD1 PD4 PD6 PD7 |
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