MC68L300EC16/D

19

NOTES:

1. All AC timing is shown with respect to 20% VDD and 70% VDD levels unless otherwise noted.

2. For high time, n = External SCK rise time; for low time, n = External SCK fall time.

Table 9 QSPI Timing

(V

DD

and V

DDSYN

= 3.0 to 3.6Vdc, V

SS

= 0 Vdc, T

A

= T

L

to T

H , 100 pF load on all QSPI pins)

1

Num

Function

Symbol

Min

Max

Unit

1

Operating Frequency

Master

Slave

fop

DC

DC

1/4

1/4

fsys

fsys

2

Cycle Time

Master

Slave

tqcyc

4

4

510

—

tcyc

tcyc

3

Enable Lead Time

Master

Slave

tlead

2

2

128

—

tcyc

tcyc

4

Enable Lag Time

Master

Slave

tlag

—

2

1/2

—

SCK

tcyc

5

Clock (SCK) High or Low Time

Master

Slave2

tsw

2 tcyc – 60

2 tcyc – n

255 tcyc

—

ns

ns

6

Sequential Transfer Delay

Master

Slave (Does Not Require Deselect)

ttd

17

13

8192

—

tcyc

tcyc

7

Data Setup Time (Inputs)

Master

Slave

tsu

30

20

—

—

ns

ns

8

Data Hold Time (Inputs)

Master

Slave

thi

0

20

—

—

ns

ns

9

Slave Access Time

ta

—1

tcyc

10

Slave MISO Disable Time

tdis

—2

tcyc

11

Data Valid (after SCK Edge)

Master

Slave

tv

—

—

50

50

ns

ns

12

Data Hold Time (Outputs)

Master

Slave

tho

0

0

—

—

ns

ns

13

Rise Time

Input

Output

tri

tro

—

—

2

30

µs

ns

14

Fall Time

Input

Output

tfi

tfo

—

—

2

30

µs

ns

Freescale Semiconductor, Inc.

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