17

ICS9LPRS365

Advance Information

1218—09/09/09

FSLC

2

B0b7

FSLB

1

B0b6

FSLA

1

B0b5

CPU

MHz

SRC

MHz

PCI

MHz

REF

MHz

USB

MHz

DOT

MHz

000

266.66

001

133.33

010

200.00

011

166.66

100

333.33

101

100.00

110

400.00

111

1. FS

LA and FSLB are low-threshold inputs.Please see VIL_FS and VIH_FS specifications in

the Input/Supply/Common Output Parameters Table for correct values.

Also refer to the Test Clarification Table.

2. FS

LC is a three-level input. Please see the VIL_FS and VIH_FS

specifications in the Input/Supply/Common Output Parameters Table for correct values.

Table 1: CPU Frequency Select Table

96.00

100.00

33.33

14.318

48.00

Reserved

Pin17 (TSSOP)

/ Pin24 (MLF)

Pin18 (TSSOP)

/ Pin25 (MLF)

Spread

MHz

MHz

%

00

0

0

0

0

0

1

100.00

100.00

0.5% Down Spread

SRCCLK1 from SRC_MAIN

0

0

1

0

100.00

100.00

0.5% Down Spread

Only SRCCLK1 from PLL3

0

0

1

1

100.00

100.00

1% Down Spread

Only SRCCLK1 from PLL3

0

1

0

0

100.00

100.00

1.5% Down Spread

Only SRCCLK1 from PLL3

0

1

0

1

100.00

100.00

2% Down Spread

Only SRCCLK1 from PLL3

0

1

1

0

100.00

100.00

2.5% Down Spread

Only SRCCLK1 from PLL3

01

1

1

N/A

N/A

N/A

N/A

1

0

0

0

24.576

24.576

None

24.576Mhz on SE1 and SE2

1

0

0

1

24.576

98.304

None

24.576Mhz on SE1, 98.304Mhz on SE2

1

0

1

0

98.304

98.304

None

98.304Mhz on SE1 and SE2

1

0

1

1

27.000

27.000

None

27Mhz on SE1 and SE2

1

1

0

0

25.000

25.000

None

25Mhz on SE1 and SE2

11

0

1

N/A

N/A

N/A

N/A

11

1

0

N/A

N/A

N/A

N/A

11

1

1

N/A

N/A

N/A

N/A

Comment

PLL 3 disabled

B1b1

B1b4

B1b3

B1b2

Table 2: PLL3 Quick Configuration