14

ICS9LPRS365

Advance Information

1218—09/09/09

Intentional PCI Clock to Clock Delay

200 ps nominal steps

PCI0

PCI1

PCI2

PCI3

PCI4

PCI_F5

1.0ns

Electrical Characteristics - PCICLK/PCICLK_F

PARAMETER

SYMBOL

CONDITIONS

MIN

MAX

UNITS

NOTES

Long Accuracy

ppm

see Tperiod min-max values

-300

300

ppm

1,2

33.33MHz output nominal

30.00900

ns

2

33.33MHz output spread

30.15980

ns

2

Absolute min/max period

T

abs

33.33MHz output nominal/spread

29.49100

30.65980

ns

2

Output High Voltage

V

OH

I

OH = -1 mA

2.4

V

1

Output Low Voltage

V

OL

I

OL = 1 mA

0.4

V

1

V

OH @MIN = 1.0 V

-33

mA

1

V

OH@MAX = 3.135 V

-33

mA

1

V

OL @ MIN = 1.95 V

30

mA

1

V

OL @ MAX = 0.4 V

38

mA

1

Rising Edge Slew Rate

t

SLR

Measured from 0.8 to 2.0 V

1

4

V/ns

1

Falling Edge Slew Rate

t

FLR

Measured from 2.0 to 0.8 V

1

4

V/ns

1

Duty Cycle

d

t1

V

T = 1.5 V

45

55

%

1

Skew

t

skew

V

T = 1.5 V

250

ps

1

Intentional PCI-PCI delay

t

delay

V

T = 1.5 V

ps

1,3

Jitter, Cycle to cycle

t

jcyc-cyc

V

T = 1.5 V

500

ps

1

*T

A = 0 - 70°C; VDD = 3.3 V +/-5%

1Guaranteed by design and characterization, not 100% tested in production.

2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz

Output High Current

I

OH

Output Low Current

I

OL

29.99100

T

period

3 See PCI Clock-to-Clock Delay Figure

200 nominal

Clock period