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PCA9547 датащи(PDF) 16 Page - Texas Instruments

номер детали PCA9547
подробное описание детали  8-channel I2C-bus multiplexer with reset
PDF  26 Pages
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производитель  TI [Texas Instruments]
домашняя страница  http://www.ti.com
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PCA9547 датащи(HTML) 16 Page - Texas Instruments

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PCA9547_2
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 02 — 12 September 2006
16 of 26
Philips Semiconductors
PCA9547
8-channel I2C-bus multiplexer with reset
11. Dynamic characteristics
[1]
Pass gate propagation delay is calculated from the 20
Ω typical R
on and the 15 pF load capacitance.
[2]
After this period, the first clock pulse is generated.
[3]
A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIH(min) of the SCL signal) in order to
bridge the undefined region of the falling edge of SCL.
[4]
Cb = total capacitance of one bus line in pF.
[5]
Measurements taken with 1 k
Ω pull-up resistor and 50 pF load.
Table 8.
Dynamic characteristics
Symbol
Parameter
Conditions
Standard-mode
I2C-bus
Fast-mode I2C-bus
Unit
Min
Max
Min
Max
tPD
propagation delay
from SDA to SDn,
or SCL to SCn
-
0.3[1]
-
0.3[1]
ns
fSCL
SCL clock frequency
0
100
0
400
kHz
tBUF
bus free time between a STOP and
START condition
4.7
-
1.3
-
µs
tHD;STA
hold time (repeated) START condition
[2]
4.0
-
0.6
-
µs
tLOW
LOW period of the SCL clock
4.7
-
1.3
-
µs
tHIGH
HIGH period of the SCL clock
4.0
-
0.6
-
µs
tSU;STA
set-up time for a repeated START
condition
4.7
-
0.6
-
µs
tSU;STO
set-up time for STOP condition
4.0
-
0.6
-
µs
tHD;DAT
data hold time
0[3]
3.45
0[3]
0.9
µs
tSU;DAT
data set-up time
250
-
100
-
ns
tr
rise time of both SDA and SCL signals
-
1000
20 + 0.1Cb[4]
300
ns
tf
fall time of both SDA and SCL signals
-
300
20 + 0.1Cb[4]
300
µs
Cb
capacitive load for each bus line
-
400
-
400
µs
tSP
pulse width of spikes that must be
suppressed by the input filter
-
50
-
50
ns
tVD;DAT
data valid time
HIGH-to-LOW
[5]
-1
-
1
µs
LOW-to-HIGH
[5]
-
0.6
-
0.6
µs
tVD:ACK
data valid acknowledge time
-
1
-
1
µs
RESET
tw(rst)L
LOW-level reset time
4
-
4
-
ns
trst
reset time
SDA clear
500
-
500
-
ns
trec(rst)
reset recovery time
0
-
0
-
ns



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