ICS9DB423B

4-OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1, GEN2, AND QPI

IDT®

4-OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1, GEN2, AND QPI

12

ICS9DB423B

REV E 091812

SMBus Table: Frequency Select Register, READ/WRITE ADDRESS (DC/DD)

Pin #

Name

Control Function

Type0

1

Default

Bit 7

PD_Mode

PD# drive mode

RW

driven

Hi-Z

0

Bit 6

STOP_Mode

DIF_Stop# drive mode

RW

driven

Hi-Z

0

Bit 5

PD_Polarity

Select PD polarity

RW

Low

High

0

Bit 4

X

Bit 3

BYPASS#1

BYPASS#/PLL1

RW

Input

Bit 2

PLL_BW#

Select PLL BW

RW

High BW

Low BW

1

Bit 1

BYPASS#0

BYPASS#/PLL0

RW

Input

Bit 0

SRC_DIV#

SRC Divide by 2 Select

RW

x/2

x/1

1

SMBus Table: Output Control Register

Pin #

Name

Control Function

Type0

1

Default

Bit 7

1

Bit 6

DIF_6

Output Enable

RW

Disable

Enable

1

Bit 5

DIF_5

Output Enable

RW

Disable

Enable

1

Bit 4

1

Bit 3

1

Bit 2

DIF_2

Output Enable

RW

Disable

Enable

1

Bit 1

DIF_1

Output Enable

RW

Disable

Enable

1

Bit 0

1

NOTE: The SMBus Output Enable Bit must be '1' AND the respective OE pin must be active for the output to run!

SMBus Table: OE Pin Control Register

Pin #

Name

Control Function

Type0

1

Default

Bit 7

0

Bit 6

DIF_6

DIF_6 Stoppable with DIFSTOP

RW

Free-run

Stoppable

0

Bit 5

DIF_5

DIF_5 Stoppable with DIFSTOP

RW

Free-run

Stoppable

0

Bit 4

0

Bit 3

0

Bit 2

DIF_2

DIF_2 Stoppable with DIFSTOP

RW

Free-run

Stoppable

0

Bit 1

DIF_1

DIF_1 Stoppable with DIFSTOP

RW

Free-run

Stoppable

0

Bit 0

0

SMBus Table: Reserved Register

Pin #

Name

Control Function

Type0

1

Default

Bit 7

X

Bit 6

X

Bit 5

X

Bit 4

X

Bit 3

X

Bit 2

X

Bit 1

X

Bit 0

X

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Byte 3

Byte 2

Reserved

19,20

9,10

6,7

22,23

Byte 1

22,23

19,20

9,10

6,7

Byte 0

-

-

-

-

-

-

-

-

See Bypass Readback

Table

See Bypass Readback

Table

Reserved