ICS9DB423B

4-OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1, GEN2, AND QPI

IDT®

4-OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1, GEN2, AND QPI

6

ICS9DB423B

REV E 091812

Electrical Characteristics–Input/Supply/Common Output Parameters

TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Input High Voltage

VIH

3.3 V +/-5%

2

VDD + 0.3

V

Input Low Voltage

VIL

3.3 V +/-5%

GND - 0.3

0.8

V

Input High Current

IIH

VIN = VDD

-5

5

uA

IIL1

VIN = 0 V; Inputs with no pull-up resistors

-5

uA

IIL2

VIN = 0 V; Inputs with pull-up resistors

-200

uA

Operating Supply Current

IDD3.3OP

Full Active, CL = Full load;

200

mA

all diff pairs driven

60

mA

all differential pairs tri-stated

6

mA

FiPLL

PCIe Mode (Bypass/133/100= 1)

50

100.00

110

MHz

FiPLL

QPI Mode (Bypass/133/100= M)

67

133.33

140

MHz

FiBYPASS

Bypass Mode (Bypass/133/100= 0)

33

400

MHz

Pin Inductance

Lpin

7nH

CIN

Logic Inputs, except SRC_IN

1.5

5

pF

CINSRC_IN

SRC_IN differential clock inputs

1.5

2.7

pF

COUT

Output pin capacitance

6

pF

-3dB point in High BW Mode

2

3

4

MHz

-3dB point in Low BW Mode

0.7

1

1.4

MHz

PLL Jitter Peaking

tJPEAK

Peak Pass band Gain

1.5

2

dB

Clk Stabilization

TSTAB

From VDD Power-Up and after input clock

stabilization or de-assertion of PD# to 1st clock

1ms

Input SS Modulation

Frequency

fMODIN

Allowable Frequency

(Triangular Modulation)

30

33

kHz

OE# Latency

tLATOE#

DIF start after OE# assertion

DIF stop after OE# deassertion

1

3

cycles

Tdrive_DIF_Stop#

tDRVSTP

DIF output enable after

DIF_Stop# de-assertion

10

ns

Tdrive_PD#

tDRVPD

DIF output enable after

PD# de-assertion

300

us

Tfall

tF

Fall time of PD# and DIF_Stop#

5

ns

Trise

tR

Rise time of PD# and DIF_Stop#

5

ns

SMBus Voltage

VMAX

Maximum input voltage

5.5

V

Low-level Output Voltage

VOL

@ IPULLUP

0.4

V

Current sinking at VOL

IPULLUP

4mA

SCLK/SDATA

Clock/Data Rise Time

tRSMB

(Max VIL - 0.15) to

(Min VIH + 0.15)

1000

ns

SCLK/SDATA

Clock/Data Fall Time

tFSMB

(Min VIH + 0.15) to

(Max VIL - 0.15)

300

ns

SMBus Operating Frequency

fMAXSMB

Maximum SMBus operating frequency

100

kHz

1Guaranteed by design and characterization, not 100% tested in production.

2See timing diagrams for timing requirements.

5The differential input clock must be running for the SMBus to be active

IDD3.3PD

3Time from deassertion until outputs are >200 mV

Input Low Current

Powerdown Current

PLL Bandwidth

BW

Input Frequency

Capacitance

4SRC_IN input