P-Channel Logic Level Enhancement Mode

Field Effect Transistor

REV 1.1

1

N-21-4

PECH1EU

PDFN 3.3x3.3S

Halogen-free & Lead-Free

NIKO-SEM

G

D

D

D

D

S

S

S

#1

Features

• Pb−Free, Halogen Free and RoHS compliant.

• Low R

DS(on) to Minimize Conduction Losses.

• Ohmic Region Good R

DS(on) Ratio.

• Optimized Gate Charge to Minimize Switching Losses.

• 100% UIS and Rg Tested.

• Products Integrated ESD diode with ESD Protected.

Applications

• Protection Circuits Applications.

• Logic/Load Switch Circuits Applications.

ABSOLUTE MAXIMUM RATINGS (TA = 25 °C Unless Otherwise Noted)

PARAMETERS/TEST CONDITIONS

SYMBOL

LIMITS

UNITS

Drain-Source Voltage

VDS

-30

V

Gate-Source Voltage

VGS

±25

V

Continuous Drain Current

4

TC = 25 °C

ID

-50

A

TC = 100 °C

-46

TA = 25 °C

-17

TA = 70 °C

-13

Pulsed Drain Current

1

IDM

-187

Avalanche Current

IAS

-54

Avalanche Energy

L = 0.1mH

EAS

145

mJ

Power Dissipation

3

TC = 25 °C

PD

57

W

TC = 100 °C

23

TA = 25 °C

3.1

TA = 70 °C

2

Junction & Storage Temperature Range

Tj, Tstg

-55 to 150

°C

PRODUCT SUMMARY

V(BR)DSS

RDS(ON)

ID

-30V

6.1mΩ

-50A

G. GATE

D. DRAIN

S. SOURCE