ADM1063ASU datasheet(19/36 Pages) AD

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ADM1063

Rev. 0 | Page 19 of 36

SEQUENCE DETECTOR

The sequence detector block is used to detect when a step in a

sequence has been completed. It looks for one of the inputs to

the SE to change state and is most often used as the gate for

successful progress through a power-up or power-down sequence.

A timer block is included in this detector, which can insert delays

into a power-up or power-down sequence if required. Timer

delays can be set from 10 µs to 400 ms. Figure 28 is a block

diagram of the sequence detector.

SUPPLY FAULT

DETECTION

LOGIC INPUT CHANGE

OR FAULT DETECTION

WARNINGS

FORCE FLOW

(UNCONDITIONAL JUMP)

VP1

VX5

INVERT

SEQUENCE

DETECTOR

SELECT

TIMER

Figure 28. Sequence Detector Block Diagram

The sequence detector can also help to identify monitoring

faults. In the sample application shown in Figure 27, the FSEL1

and FSEL2 states identify which of the VP1,VP2, or VP3 pins

has faulted, and then they take the appropriate action.

MONITORING FAULT DETECTOR

The monitoring fault detector block is used to detect a failure

on an input. The logical function implementing this is a wide

OR gate, which can detect when an input deviates from its

expected condition. The clearest demonstration of the use of

this block is in the POWER_GOOD state, where the monitor

block indicates that a failure on one or more of the VP1, VP2,

or VP3 inputs has occurred.

No programmable delay is available in this block, because the

triggering of a fault condition is likely to be caused when a supply

falls out of tolerance. In this situation, the user should react as

quickly as possible. Some latency occurs when moving out of

this state, because it takes a finite amount of time (~20 µs) for the

state configuration to download from EEPROM into the SE.

Figure 29 is a block diagram of the monitoring fault detector.

SUPPLY FAULT

DETECTION

LOGIC INPUT CHANGE

OR FAULT DETECTION

VP1

VX5

MONITORING FAULT

DETECTOR

MASK

SENSE

1-BIT FAULT

DETECTOR

FAULT

WARNINGS

MASK

1-BIT FAULT

DETECTOR

FAULT

MASK

SENSE

1-BIT FAULT

DETECTOR

FAULT

Figure 29. Monitoring Fault Detector Block Diagram

TIMEOUT DETECTOR

The timeout detector allows the user to trap a failure and,

thus ensuring proper progress through a power-up or power-

down sequence.

In the sample application shown in Figure 27, the timeout next-

state transition is from the EN3V3 and EN2V5 states. For the

EN3V3 state, the signal 3V3ON is asserted on the PDO1 output

pin upon entry to this state to turn on a 3.3 V supply. This supply

rail is connected to the VP2 pin, and the sequence detector looks

for the VP2 pin to go above its UV threshold, which is set in the

supply fault detector (SFD) attached to that pin.

The power-up sequence progresses when this change is detected.

If, however, the supply fails (perhaps due to a short circuit over-

loading this supply), the timeout block traps the problem. In this

example, if the 3.3 V supply fails within 10 ms, the SE moves to

the DIS3V3 state and turns off this supply by bringing PDO1

low. It also indicates that a fault has occurred by taking PDO3

high. Timeout delays of 100 µs to 400 ms can be programmed.

FAULT REPORTING

The ADM1063 has a fault latch for recording faults. Two registers

are set aside for this purpose. A single bit is assigned to each

input of the device, and a fault on that input sets the relevant

bit. The contents of the fault register can be read out over the

SMBus to determine which input(s) faulted. The fault register

can be enabled/disabled in each state. This ensures that only

real faults are captured and not, for example, undervoltage

trips when the SE is executing a power-down sequence.

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