DSP56321RM datasheet(48/84 Pages) NXP

номер детали	DSP56321RM

подробное описание детали	24-Bit Digital Signal Processor

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DSP56321 Technical Data, Rev. 11

2-28

Freescale Semiconductor

Specifications

2.4.11 JTAG Timing

Table 2-14.

JTAG Timing

No.

Characteristics

All frequencies

Unit

Min

Max

500

TCK frequency of operation (1/(T

C ×

3); absolute maximum 22 MHz)

0.0

22.0

MHz

501

TCK cycle time in Crystal mode

45.0

—

502

TCK clock pulse width measured at 1.6 V

20.0

—

503

TCK rise and fall times

0.0

3.0

504

Boundary scan input data setup time

5.0

—

505

Boundary scan input data hold time

24.0

—

506

TCK low to output data valid

0.0

40.0

507

TCK low to output high impedance

0.0

40.0

508

TMS, TDI data setup time

5.0

—

509

TMS, TDI data hold time

25.0

—

510

TCK low to TDO data valid

0.0

44.0

511

TCK low to TDO high impedance

0.0

44.0

512

TRST assert time

100.0

—

513

TRST setup time to TCK low

40.0

—

Notes:

VCCQH = 3.3 V ± 0.3 V, VCCQL = 1.6 V ± 0.1 V; TJ = –40°C to +100 °C, CL = 50 pF.

All timings apply to OnCE module data transfers because it uses the JTAG port as an interface.

Figure 2-28.

Test Clock Input Timing Diagram

TCK

(Input)

VIH

VIL

501

502

503

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