DSP56321RM datasheet(24/84 Pages) NXP

24 / 84 page

DSP56321 Technical Data, Rev. 11

2-4

Freescale Semiconductor

Specifications

2.4.2

External Clock Operation

The DSP56321 system clock is derived from the on-chip oscillator or is externally supplied. To use the on-chip

oscillator, connect a crystal and associated resistor/capacitor components to EXTAL and XTAL; an example is

shown in Figure 2-1.

Internal clock low period

•

With DPLL disabled

•

With DPLL enabled

—

0.49

× TC

ETC

—

0.51

× TC

Note:

Ef = External frequency; MF = Multiplication Factor = MFI + MFN/MFD; PDF = Predivision Factor;

DF = Division Factor; TC = Internal clock cycle; ETC = External clock cycle; TH = Internal clock high;

TL = Internal clock low

Figure 2-1.

Crystal Oscillator Circuits

Table 2-5.

External Clock Operation

No.

Characteristics

Symbol

200 MHz

220 MHz

240 MHz

275 MHz

Min

Max

Min

Max

Min

Max

Min

Max

Frequency of EXTAL

(EXTAL Pin Frequency)1

•

With DPLL disabled

•

With DPLL enabled

DEFR = PDF

× PDFR

0 MHz

16 MHz

200 MHz

0 MHz

16 MHz

220 MHz

0 MHz

16 MHz

240 MHz

0 MHz

16 MHz

275 MHz

EXTAL input high3

•

With DPLL disabled

(46.7%–53.3% duty

cycle4)

•

With DPLL enabled

(42.5%–57.5% duty

cycle4)

ETH

2.34 ns

2.13 ns

∞

35.9 ns

2.12 ns

1.93 ns

∞

35.9 ns

1.95 ns

1.77 ns

∞

35.9 ns

1.70 ns

1.55 ns

∞

35.9 ns

EXTAL input low

•

With DPLL disabled

(46.7%–53.3% duty

cycle

•

With DPLL enabled

(42.5%–57.5% duty

cycle

ETL

2.34 ns

2.13 ns

∞

35.9 ns

2.12ns

1.93 ns

∞

35.9 ns

1.95 ns

1.77 ns

∞

35.9 ns

1.70 ns

1.55 ns

∞

35.9 ns

Table 2-4.

Internal Clocks (Continued)

Characteristics

Symbol

Expression

Min

Typ

Max

Suggested Component Values:

fOSC = 16–32 MHz

R = 1 M

Ω ± 10%

C = 10 pF

± 10%

Calculations are for a 16–32 MHz crystal with the following parameters:

•

shunt capacitance (C0) of 5.2–7.3 pF,

•

series resistance of 5–15

Ω, and

•

drive level of 2 mW.

XTAL1

Fundamental Frequency

Crystal Oscillator

XTAL

EXTAL

Note: Make sure that in the PCTL Register:

•XTLD (bit 2) = 0

DSP56321RM датащи(PDF) 24 Page - NXP Semiconductors

DSP56321RM датащи(HTML) 24 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84

датащи скачать

ссылки URL