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S5320 – PCI Match Maker: Signal Description

DS1656

AMCC Confidential and Proprietary

Revision 5.03 – June 14, 2006

Data Sheet

Table 9. Add-On Bus General Pins

Signal

Type

Description

SYSRST#

out

System Reset. An active-low buffered PCI bus RST# output signal. The signal is asynchro-

nous and can be asserted through software from the PCI host interface.

BPCLK

out

Buffered PCI Clock. This output is a buffered form of the PCI bus clock and has all of the

behavioral characteristics of the PCI clock (i.e., DC-to-33 MHz capability).

ADCLK

Add-On Clock. All internal S5320 Add-On bus logic is synchronous to this clock. The clock

is asynchronous to the PCI bus logic unless connected to the BPCLK signal.

IRQ#

out

Interrupt Request. This output signals to Add-On logic that a significant event has occurred

as a result of activity within the S5320.

ADDINT#

Add-On interrupt. When enabled and asserted, this input will cause a PCI bus interrupt by

driving INTA# low. The input is level sensitive and can be driven by multiple sources. This

signal is connected to an internal 50k Ohm pull-up.

FLT#

Float. Floats all S5320 output signals when asserted. This signal is connected to an internal

50k Ohm pull-up

Pin 125

For factory use only. Must be left open. (RSVD1)

Pin 139

For factory use only. Must be left open. (RSVD2)

Pin 140

For factory use only. Must be left open. (RSVD3)

Pin 156

For factory use only. Must be left open. (RSVD4)

Pin 134

For factory use only. Must be left open. (RSVD5)

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