CS5320 datasheet(137/160 Pages) AMCC

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S5320 – PCI Match Maker: Pass-Thru Operation

Revision 5.03 – June 14, 2006

AMCC Confidential and Proprietary

DS1656

137

Data Sheet

Figure 79. Active Mode PCI Read

Figure 79 shows a Pass-Thru read cycle with 0 wait

states for a 16-bit region. The PTBE[3:0]# signals are

used by the Add-On device to determine validity of the

current word cycle and also, which word of a long word

is currently being driven by the S5320. PTBE[3:0]#

encoding of Ch indicates the least significant 16-bit

portion of the 32-bit PCI data word is on the DQ[15:0]

bus. PTBE[3:0]# encoding of 3h indicates the most

significant 16-bit portion of the 32-bit PCI data word is

on the DQ[15:0] bus. PTADR# is shown as disabled in

Figure 79.

Figure 80 shows a Pass-Thru write cycle with 0 wait

states for a 16-bit region. PTADR# is disabled.

If the Add-On bus size is 8 bits, then the S5320 will

assert DXFR# 4 times for each 32-bit PCI word The

first completion is for byte 0, the second is for byte 1,

the third is for byte 3, and the fourth DXFR# assertion

is for byte 4 of a 32-bit word. If the current PCI access

has less than four bytes valid (PCI BE[3:0]# encoding

is not 0h), then the S5320 will still assert a 4-cycle

completion but one or more of them will not contain

valid data (PTBE[3:0]# = Fh).

As in Passive mode, in Active mode, the word read/

write order is determined by the Endian conversion

programmed into the S5320.

Figure 80. Active Mode PCI Write

Figure 81 shows a Pass-Thru write cycle with 0 wait

states for an 8-bit region. The PTBE[3:0]# signals are

used by the Add-On device to determine validity of the

current byte cycle and also, which byte of a long word

is currently being driven by the S5320. PTADR# is

enabled as an output.

CONFIGURATION

The S5320 Pass-Thru interface utilizes four Base

Address Registers (BADR1:4). Each Base Address

tents of these registers during initialization determine

the characteristics of that particular Pass-Thru region.

Each region can be mapped to memory or I/O space.

Memory mapped devices can, optionally, be mapped

below 1 Mbyte and can be identified as prefetchable.

Both memory and I/O regions can be configured as 8,

16 or 32 bits wide.

Base Address Registers are loaded during initializa-

tion from the external non-volatile boot device. Without

an external boot device, the default value for the

BADR registers is zero (region disabled). The Base

Address Registers are the only registers that define

Pass-Thru operation. Consequently, the Pass-Thru

interface cannot be used without an external non-vola-

tile boot device.

ADCLK

PTATN#

PTBURST#

PTNUM[1:0]

PTWR

PTBE[3:0]

DXFR#

DQ[15:0]

PTWAIT#

LOW

HIGH

PTADR#

234

ADCLK

PTATN#

PTBURST#

PTNUM[1:0]

PTWR

PTBE[3:0]

DXFR#

DQ[15:0]

PTWAIT#

LOW

HIGH

PTADR#

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