ADP3198 datasheet(30/32 Pages) AD

30 / 32 page

ADP3198

Rev. A | Page 30 of 32

AC Load Line Setting

11. Remove the dc load from the circuit and hook up the

dynamic load.

12. Hook up the scope to the output voltage and set it to dc

coupling with the time scale at 100 μs/div.

13. Set the dynamic load for a transient step of about 40 A at

1 kHz with 50% duty cycle.

14. Measure the output waveform (use dc offset on scope to see

the waveform). Try to use a vertical scale of 100 mV/div or

finer. This waveform should look similar to Figure 17.

VDCDRP

VACDRP

Figure 17. AC Load Line Waveform

15. Use the horizontal cursors to measure VACDRP and VDCDRP as

shown in Figure 17. Do not measure the undershoot or

overshoot that happens immediately after this step.

16. If VACDRP and VDCDRP are different by more than a few

millivolts, use Equation 49 to adjust CCS. Users may need to

parallel different values to get the right one because limited

standard capacitor values are available. It is a good idea to

have locations for two capacitors in the layout for this.

()

DCDRP

ACDRP

OLD

NEW

(49)

17. Repeat Step 11 to Step 13 and repeat the adjustments, if

necessary. Once complete, do not change CCS for the

remainder of the procedure. Set the dynamic load step to

maximum step size. Do not use a step size larger than

needed. Verify that the output waveform is square, which

means that VACDRP and VDCDRP are equal.

Initial Transient Setting

18. With the dynamic load still set at the maximum step size,

expand the scope time scale to either 2 μs/div or 5 μs/div.

The waveform can have two overshoots and one minor

undershoot (see Figure 18). Here, VDROOP is the final

desired value.

VDROOP

VTRAN2

VTRAN1

Figure 18. Transient Setting Waveform

19. If both overshoots are larger than desired, try making

the adjustments using the following suggestions:

•

Make the ramp resistor larger by 25% (RRAMP)

•

For VTRAN1, increase CB or increase the switching

frequency

•

For VTRAN2, increase RA and decrease CA by 25%

If these adjustments do not change the response, the design

is limited by the output decoupling. Check the output

response every time a change is made, and check the switch-

ing nodes to ensure that the response is still stable.

20. For load release (see Figure 19), if VTRANREL is larger

than the allowed overshoot, there is not enough output

capacitance. Either more capacitance is needed, or the

inductor values need to be made smaller. When changing

inductors, start the design again using a spreadsheet and

this tuning procedure.

VDROOP

VTRANREL

Figure 19. Transient Setting Waveform

Because the ADP3198 turns off all of the phases (switches

inductors to ground), no ripple voltage is present during load

release. Therefore, the user does not have to add headroom for

ripple. This allows load release VTRANREL to be larger than VTRAN1

by the amount of ripple, and still meet specifications.

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