ADP3198 datasheet(23/32 Pages) AD

23 / 32 page

ADP3198

Rev. A | Page 23 of 32

Compute the relative values for RCS1, RCS2, and RTH using

()

(

)

CS2

−

(8)

()

CS2

CS1

−

(9)

CS1

CS2

−

(10)

Calculate RTH = rTH × RCS, then select the closest value of

thermistor available. Also, compute a scaling factor (k)

based on the ratio of the actual thermistor value used

relative to the computed one.

()

CALCULATED

ACTUAL

k =

(11)

Calculate values for RCS1 and RCS2 using Equation 12 and 13.

CS1

(12)

()

(

)

(

)

CS2

−

(13)

In this example, RCS is calculated to be 114 kΩ. Look for an

available 100 kΩ thermistor, 0603 size. One such thermistor

is the Vishay NTHS0603N01N1003JR NTC thermistor with

A = 0.3602 and B = 0.09174. From these values, rCS1 = 0.3795,

rCS2 = 0.7195, and rTH = 1.075.

Solving for RTH yields 122.55 kΩ, so 100 kΩ is chosen, making

k = 0.816. Next, find RCS1 and RCS2 to be 35.3 kΩ and 87.9 kΩ.

Finally, choose the closest 1% resistor values, which yields a

choice of 35.7 kΩ and 88.7 kΩ.

Load Line Setting

For load line values greater than 1 mΩ, RCSA can be set equal

to RO, and the LLSET pin can be directly connected to the

CSCOMP pin. When the load line value needs to be less than

1 mΩ, two additional resistors are required. Figure 12 shows

the placement of these resistors.

CSSUM

CSCOMP

CSREF

ADP3198

LLSET

QLL

OPTIONAL LOAD LINE

SELECT SWITCH

RLL2

RLL1

Figure 12. Load Line Setting Resistors

The two resistors RLL1 and RLL2 set up a divider between the

CSCOMP pin and CSREF pin. This resistor divider is input into

the LLSET pin to set the load line slope RO of the VR according

to the following equation:

CSA

(14)

The resistor values for

RLL1 and RLL2 are limited by two factors.

•

The minimum value is based upon the loading of the

CSCOMP pin. This pin’s drive capability is 500 μA and the

majority of this should be allocated to the CSA feedback. If

the current through RLL1 and RLL2 is limited to 10% of this

(50 μA), the following limit can be placed for the minimum

value for RLL1 and RLL2:

−

≥

CSA

LIM

(15)

Here, ILIM is the current-limit current, which is the

maximum signal level that the CSA responds to.

•

The maximum value is based upon minimizing induced dc

offset errors based on the bias current of the LLSET pin. To

keep the induced dc error less than 1 mV, which makes this

error statistically negligible, place the following limit of the

parallel combination of RLL1 and RLL2:

120

−

≤

= 8.33 kΩ

(16)

It is best to select the resistor values to minimize their values to

reduce the noise and parasitic susceptibility of the feedback path.

By combining Equation 16 with Equation 14 and selecting

minimum values for the resistors, the following equations result:

LIM

(17)

CSA

⎟⎟

⎠

⎞

⎜⎜

⎝

⎛

−

(18)

Therefore, both RLL1 and RLL2 need to be in parallel and less than

8.33 kΩ.

Another useful feature for some VR applications is the ability to

select different load lines. Figure 12 shows an optional MOSFET

switch that allows this feature. Here, design for RCSA = RO(MAX)

(selected with QLL on) and then use Equation 14 to set RO = RO(MIN)

(selected with QLL off).

For this design, RCSA = RO = 1 mΩ. As a result, connect LLSET

directly to CSCOMP; the RLL1 and RLL2 resistors are not needed.

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