IRMCS2033

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17

Address Byte

HP_A = 1

Data Byte 0

HP_A = 0

…………….

HP_A = 0

Data Byte N

HP_A = 0

Host Parallel Data Transfer Format

Figure 9 and Table 2 show read cycle timing for the host parallel interface. Figure 10 and Table 3 show write cycle

timing.

HP_nWE

HP_D [7:0]

HP_nOE

HP_A

HP_nCS

t

HPCSN

VALID

t

HPWENS

t

HPAS

t

HPDZ

t

HPOEN

t

AHPD

t

HPOENS

t

HPA

t

HPZD

Figure 9. Host Parallel Read Cycle Timing

SYMBOL

DESCRIPTION

MIN

MAX

UNIT

S

NOTE

HP_nCS Period

70

ns

HP_nWE Setup

40

ns

Note 3

HP_A Setup

40

ns

HP_D [7:0] Access

60

105

ns

HP_D [7:0] Active

0

9

ns

HP_D [7:0] High Impedance

0

6

ns

HP_nOE Setup

40

ns

Note 3

HP_nOE Period

70

ns

Table 2: Host Parallel Read Cycle Timing

Note:

1. HP_nOE, HP_nWE must be stable before the high to low transition of HP_nCS.