IRMCS2033

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16

Parallel Interface Port

IRMCS2033 provides an 8-bit parallel interface port to facilitate microprocessor interface. The interface is generic and

compatible with most common 8-bit parallel interfaces such as MCS8051, some Motorola 8-bit uP, Microchip, etc.

Figure 8 shows the connection diagram. The connector, J5, is a 2-by-10 header connector.

J5

HEADER 20

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

VCC

HP_D0

HP_D1

HP_D2

HP_D3

HP_D4

HP_D5

HP_D6

HP_D7

NA

NA

NA

NA

HP_nCS

HP_nWE

HP_nOE

HP_A

Figure 8. Parallel Interface Port

Each signal is 3.3V level and the data bus is multiplexed. Table 1 summarizes each signal definition.

Signal

Description

HP_nCS

I

Active low Host Port Chip Select

HP_nOE

I

Active Low Host Port Output Enable

HP_nWE

I

Active low Host Port Write Enable

HP_A

I

Host Port Register Address. 1 = Address register, 0 = Data Register

HP_Dn

I/O

Bidirectional Host Port data bus, where n = data bit 0 - 7

Table 1. Microprocessor Interface Module Signal Definitions

The IRMCK203 contains an address register that is updated with the Host Register address when HP_A = 1. After

each subsequent data byte is either read or written, the internal address register is incremented. The diagram below

shows that Data Bytes 0 to N would access register locations initially specified by the Address Byte. The Address

Byte with the HP_A signal can be asserted at any time.