AD12401SLASHKIT datasheet(19/28 Pages) AD

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AD12401

Rev. A | Page 19 of 28

Figure 21 displays the application of this relationship to a full-

scale, single-tone input signal on the AD12401, where the DNL

was assumed to be 0.4 LSB, and the input noise was assumed to

be 0.8 LSB rms. The vertical marker at 0.4 ps displays the SNR

at the jitter level present in the AD12401 evaluation system,

including the jitter associated with the AD12401 itself.

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

APERTURE JITTER (ps rms)

AIN = 10MHz

AIN = 65MHz

AIN = 128MHz

AIN = 180MHz

Figure 21. SNR vs. Aperture Jitter

In addition to jitter, the harmonic content of the single-ended

sine wave clock sources must be controlled. The clock source

used in the test and calibration process has a harmonic per-

formance that is better than 60 dBc. Additionally, when using

PECL or other square-wave clock sources, unstable behavior,

such as overshoot and ringing, can affect phase matching and

degrade the image spur performance.

DIGITAL OUTPUTS

The AD12401’s digital postprocessing circuit provides two

parallel, 12-bit, 200 MSPS data output buses. By providing two

output busses that operate at one half the conversion rate, the

AD12401 eliminates the need for large, expensive, high power

demultiplexing circuits. The output data format is twos com-

plement, maintaining the standard set by other high speed

ADCs, such as the AD9430 and AD6645. Data-ready signals are

provided for facilitating proper timing in the data capture circuit.

POWER SUPPLIES

The AD12401 requires three different supply voltages: a 1.5 V

supply for the digital postprocessing circuit, a 3.3 V supply to

facilitate digital I/O through the system, and a 3.8 V supply for

the analog conversion and clock distribution circuits. The

AD12401 incorporates two key features that result in solid

PSRR performance. First, on-board linear regulators are used to

provide an extra level of power supply rejection for the analog

circuits. The linear regulator used to supply the ADCs provides

an additional 60 dB of rejection at 100 kHz. Second, to address

higher frequency noise (where the linear regulators’ rejection

degrades), the AD12401 incorporates high quality ceramic

decoupling capacitors.

While this product was designed to provide good PSRR

performance, system designers need to be aware of the risks

associated with switching power supplies and consider using

linear regulators in their high speed ADC systems. Switching

power supplies typically produces both conducted and radiated

energy that result in common-/differential-mode EMI currents.

Any system that requires 12-bit performance has very little

room for errors associated with power supply EMI. For exam-

ple, a system goal of 74 dB dynamic range performance on the

AD12401 requires noise currents that are less than 4.5 μA and

noise voltages of less than 225 μV in the analog input path.

STARTUP AND RESET

The AD12401’s FPGA configuration is stored in the on-board

EPROM and loaded into the FPGA when power is applied to

the device. The RESET pin (active low) allows the user to reload

the FPGA in case of a low digital supply voltage condition or a

power supply glitch. Pulling the RESET pin low pulls the data-

ready and output bits high until the FPGA is reloaded. The

RESET pin should remain low for a minimum of 200 ns. On the

rising edge of the reset pulse, the AD12401 starts loading the

configuration into the FPGA. The reload process requires a

maximum of 87 ms to complete. Valid signals on the data-ready

pins indicate the reset process is complete. In addition, system

designers must be aware of the thermal conditions of the

AD12401 at startup. If large thermal imbalances are present, the

AD12401 can require additional time to stabilize before providing

specified image spur performance.

DR_EN

The DR_EN pin is used to synchronize the collection of data

into external buffer memories. DR_EN must be held low for a

minimum amount of time (see Table 2 through Table 4 for each

ENCODE rate) to ensure correct operation. The function shuts

off DRA and DRB until the DR_EN pin is set high again. DRA

and DRB resume on the next valid DRA after DR_EN is

released. If this feature is not required, tie this pin to 3.3 V

through a 3.74 kΩ.

OVERRANGE

The differential OROUT pins are used to determine if the

AD12401 input is overranged. OROUT timing is identical to the

Channel B data. If the OROUT pin is high, then the Channel B

data coincident with the overrange indication or the Channel A

data immediately preceding it resulted from an overrange input.

If the OROUT pin is low, the operation is normal.

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