AD12401

Rev. A | Page 12 of 28

Pin No.

Mnemonic

Description

69

DA3

Channel A Data Bit 3. Complement output bit.

70

DA2

Channel A Data Bit 2. Complement output bit.

71

DA3

Channel A Data Bit 3. True output bit.

72

DA2

Channel A Data Bit 2. True output bit.

73

DA1

Channel A Data Bit 1. Complement output bit.

74

DA0

Channel A Data Bit 0. Complement output bit. DA0 is LSB.

75

DA1

Channel A Data Bit 1. True output bit.

76

DA0

Channel A Data Bit 0. True output bit. DA0 is LSB.

77

DR_EN

Data Ready Enable, Typically DNC. See the DR_EN section.

78

DRA

Channel A Data Ready. Complement output.

80

DRA

Channel A Data Ready. True output.

103

H/L GAIN

Gain Select Pin. Ground for low gain mode (KWS); pull up to 3.3 V for high gain mode (JWS).

81 to 95, 109 to 112,

129 to 1321

AGND

Analog Ground.

113 to 120

VA

Analog Supply, 3.7 V.

121 to 1281

DGND

Digital Ground.