APR9SLASHD datasheet(48/101 Pages) NXP

48 / 101 page

2-30

DSP56001A/D, Rev. 1

MOTOROLA

DSP56001A

External Bus Synchronous Timing

EXTERNAL BUS SYNCHRONOUS TIMING

VCC = 5.0 V ± 10% for 27 MHz, VCC = 5.0 Vdc ± 5% for 33 MHz,

TJ = -40˚ to +105˚ C, CL = 50 pF + 1 TTL loads

Capacitance Derating

: The DSP56001A external bus timing specifications are designed and

tested at the maximum capacitive load of 50 pF, including stray capacitance. Typically, the drive

capability of the external bus pins (A0–A15, D0–D23, PS, DS, RD, WR, X/Y) derates linearly at 1

ns per 12 pF of additional capacitance from 50 pF to 250 pF of loading. Port B and C pins (HI,

SCI, SSI) derate linearly at 1 ns per 5 pF of additional capacitance from 50 pF to 250 pF of loading.

Active-low lines should be pulled up in a manner consistent with the AC and DC specifications.

Table 2-14

External Bus Synchronous Timing

Num

Characteristics

27 MHz

33 MHz

Unit

Min

Max

Min

Max

140

Clk Low transition to

Address Valid

—19—19

141

Clk High transition to WR

Assertion(See Note 1, 2)

•

WS=0

•

WS>0

TH + 17

142

Clk High transition to WR

Deassertion

516513

143

Clk High transition to RD

Assertion

016016

144

Clk High transition to RD

Deassertion

10.5

145

Clk Low transition to Data-

Out Valid

—19—19

146

Clk Low transition to Data-

Out Invalid (See Note 3)

—

3.5

—

147

Data-In Valid to Clk High

transition (Setup)

4—4—

148

Clk High transition to

Data-In Invalid (Hold)

12—12—

149

Clk Low transition to

Address Invalid (See Note 3)

2—2—

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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