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DSP56307/D датащи(PDF) 70 Page - NXP Semiconductors |
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DSP56307/D датащи(HTML) 70 Page - NXP Semiconductors |
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70 / 156 page ![]() 2-34 DSP56307 Technical Data MOTOROLA Specifications External Memory Interface (Port A) 180 CAS assertion to WR deassertion tWCH 1.5 × T C − 4.2 70.8 Ñ 45.8 Ñ ns 181 RAS assertion to WR deassertion tWCR 3 × T C − 4.2 145.8 Ñ 95.8 Ñ ns 182 WR assertion pulse width tWP 4.5 × T C − 4.5 220.5 Ñ 145.5 Ñ ns 183 WR assertion to RAS deassertion tRWL 4.75 × T C − 4.3 233.2 Ñ 154.0 Ñ ns 184 WR assertion to CAS deassertion tCWL 4.25 × T C − 4.3 208.2 Ñ 137.4 Ñ ns 185 Data valid to CAS assertion (write) tDS 2.25 × T C − 4.0 108.5 Ñ 71.0 Ñ ns 186 CAS assertion to data not valid (write) tDH 1.75 × T C − 4.0 83.5 Ñ 54.3 Ñ ns 187 RAS assertion to data not valid (write) tDHR 3.25 × T C − 4.0 158.5 Ñ 104.3 Ñ ns 188 WR assertion to CAS assertion tWCS 3 × T C − 4.3 145.7 Ñ 95.7 Ñ ns 189 CAS assertion to RAS assertion (refresh) tCSR 0.5 × T C − 4.0 21.0 Ñ 12.7 Ñ ns 190 RAS deassertion to CAS assertion (refresh) tRPC 1.25 × T C − 4.0 58.5 Ñ 37.7 Ñ ns 191 RD assertion to RAS deassertion tROH 4.5 × T C − 4.0 221.0 Ñ 146.0 Ñ ns 192 RD assertion to data valid tGA 4 × T C − 7.5 Ñ 192.5 Ñ 125.8 ns 193 RD deassertion to data not valid3 tGZ Ñ 0.0 Ñ 0.0 Ñ ns 194 WR assertion to data active Ñ 0.75 × T C − 0.3 37.2 Ñ 24.7 Ñ ns 195 WR deassertion to data high impedance Ñ 0.25 × T C Ñ 12.5 Ñ 8.3 ns Notes: 1. The number of wait states for out-of-page access is specified in the DCR. 2. The refresh period is specified in the DCR. 3. RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is tOFF and not tGZ. 4. Reduced DSP clock speed allows use of DRAM out-of-page access with four Wait states (see Figure 2-17). Table 2-13 DRAM Out-of-Page and Refresh Timings, Four Wait States1, 2 (Continued) No. Characteristics3 Symbol Expression 20 MHz4 30 MHz4 Unit Min Max Min Max Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com Not Recommended for New Design |
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