ISL81601 datasheet(10/54 Pages) RENESAS

10 / 54 page

FN9299 Rev.3.1

Page 10 of 53

May 27, 2021

ISL81601

2. Pin Information

2.2

Pin Descriptions

Pin #

(QFN)

Pin #

(HTSSOP)

Name

Function

BSTEN

DE Burst mode enable signal. The pin is pulled up to 5V by an internal 250k resistor in PWM and

DE mode. It is pulled low in Burst mode. The pull-down MOSFET rDS(ON) resistance is about 4.5k.

Connect this pin together in the multi-chip parallel operation application to sync all the chips

together for Burst mode operation.

FB_IN

Input voltage feedback pin for reverse direction operation. Use a resistor divider to feed the input

voltage back to this pin. When the input voltage drops to the pin voltage below 0.8V, the internal

control loop reduces the duty cycle to sink in current from output to input to keep the pin voltage

regulated at 0.8V.

Keep the pin voltage below 0.3V to disable the reverse direction operation.

When the reverse operation function is not used, tie this pin to VCC5V or SGND to set up the phase

shift for the interleaving parallel operation.

VCC5V

Output of the internal 5V linear regulator. This output supplies bias for the IC. The VCC5V pin must

always be decoupled to SGND with a minimum of 4.7µF ceramic capacitor placed very close to the

pin.

4, 22, 24,

28, 33, 37

No connection pin.

RT/SYNC

A resistor from this pin to ground adjusts the default switching frequency from 100kHz to 600kHz.

The default switching frequency of the PWM controller is determined by the resistor RT as shown in

Equation 1.

where fSW is the switching frequency in MHz.

When this pin is open or tied to VCC5V, the fSW is set to 120kHz. When this pin is tied to GND, the

fSW is set to 575kHz.

When an external clock signal is applied to this pin, the internal frequency is synchronized to the

external clock frequency.

PLL_COMP Compensation pin for the internal PLL circuit. A compensation network shown in the Figure 52 on

page 37 is required. RPLL(2.7kΩ), CPLL1 (10nF), and CPLL2 (820pF) are recommended.

714

CLKOUT/

DITHER

Dual function pin. When there is no capacitor connected to this pin, it provides a clock signal to

synchronize the other ISL81601(s). The phase shift of the clock signal is set by the FB_IN and

IMON_IN pin voltages.

When a capacitor is connected to this pin, the clock out function is disabled and the frequency dither

function is enabled before the soft-start. The capacitor is charged and discharged by internal current

sources. As the voltage on the pin ramps up and down, the oscillator frequency is modulated

between –15% and +15% of the nominal frequency set by the RT resistor. The frequency dither

function is disabled in the external Sync mode or if the RT pin is open or shorted.

SS/TRK

Dual function pin. When used for soft-starting control, a soft-start capacitor is connected from this

pin to ground. A regulated 2μA soft-starting current charges up the soft-start capacitor. the value of

the soft-start capacitor sets the output voltage ramp.

When used for tracking control, an external supply rail is configured as the master and the output

voltage of the master supply is applied to this pin using a resistor divider. The output voltage tracks

the master supply voltage.

COMP

Voltage error GM amplifier output. It sets the reference of the inner current loop. The feedback

compensation network is connected between the COMP and SGND pins. When the COMP pin is

pulled below 1V, the PWM duty cycle reduces to 0%.

FB_OUT

Output voltage feedback input. Connect FB_OUT to a resistive voltage divider between the output

and SGND to adjust the output voltage. FB_OUT pin voltage is regulated to the internal 0.8V

reference.

34.7

fSW

----------- 4.78

–



 k



(EQ. 1)

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