ISL81601 datasheet(41/54 Pages) RENESAS

41 / 54 page

FN9299 Rev.3.1

Page 41 of 53

May 27, 2021

ISL81601

5. Functional Description

VIMON_OUT2 - ViSh for U4A. The differential op amp gain and the value of the resistor between the op amp output

and the FB_OUT pin can be defined based on the current sharing accuracy and the allowed max output voltage

change caused by the current sharing loop, assuming the current sense circuit tolerance can be ignored.

The maximum allowed current sharing error can be represented by the max allowed differential op amp input. The

differential op amp outputs a maximum voltage of 5V at its maximum differential input, assuming a rail-to-rail op

amp is used. The differential op amp gain Ksh can be calculated by Equation 17.

where ΔVsh is the maximum allowed differential op amp input voltage, which is proportional to the output current

sharing error ΔIsh = |IOUT1 – IOUT2| / 2. IOUT1 and IOUT2 are the output currents of Converter 1 and 2, respectively.

ΔVsh = ΔIsh x RIM_OUT x RS_OUT x GmISEN, referring to the descriptions in “Input and Output Average Current

Monitoring and Regulation Loops” on page 30.

As shown in Figure 54 on page 40, Ksh = R23/R27 for Converter 1 and Ksh = R56/R58 for Converter 2.

The value Rsh of the resistor between the differential op amp output and the FB_OUT pin can be calculated using

Equation 18.

where ΔVOUT is the maximum allowed output voltage change caused by the current sharing loop, which is limited

by the VOUT regulation tolerance.

RFBO1 is the resistance of the upper resistor of the VOUT voltage sense divider shown in Figure 43 on page 29. As

shown in Figure 54, Rsh = R29 + R30 for Converter 1 and Rsh = R64 + R65 for Converter 2. RFBO1 = R18 for

Converter 1 and RFBO1 = R50 for Converter 2.

5.13

Gate Drivers

The ISL81601 integrates two almost identical high voltage driver pairs to drive both buck and boost MOSFET

pairs. Each driver pair consists of a gate control logic circuit, a low-side driver, a level shifter, and a high-side

driver.

The ISL81601 incorporates an adaptive dead time algorithm that optimizes operation with varying MOSFET

conditions. This algorithm provides approximately 16ns dead time between the switching of the upper and lower

MOSFETs. This dead time is adaptive and allows operation with different MOSFETs without having to externally

adjust the dead time using a resistor or capacitor. During turn-off of the lower MOSFET, the LGATE voltage is

monitored until it reaches a threshold of 1V, at which time the UGATE is released to rise. Adaptive dead time

circuitry monitors the upper MOSFET gate voltage during UGATE turn-off. When the upper MOSFET

gate-to-source voltage drops below a threshold of 1V, the LGATE is allowed to rise. Renesas recommends not

using a resistor between the driver outputs and the respective MOSFET gates, because it can interfere with the dead

time circuitry.

The low-side gate driver is supplied from VDD and provides a 3A peak sink and 2A peak source current. The

high-side gate driver can also deliver peak 3A sink and 2A source current. Gate-drive voltage for the upper

N-channel MOSFET is generated by a flying capacitor boot circuit. A boot capacitor connected from the BOOT

pin to the PHASE node provides power to the high-side MOSFET driver. As shown in Figure 55 on page 42, the

boot capacitor is charged up to VDD by an external Schottky diode during low-side MOSFET on-time (phase node

low). To limit the peak current in the Schottky diode, an external resistor can be placed between the BOOT pin and

the boot capacitor. This small series resistor also damps any oscillations caused by the resonant tank of the parasitic

inductances in the traces of the board and the FET’s input capacitance.

At start-up, the low-side MOSFET turns on first and forces PHASE to ground to charge the BOOT capacitor to 8V

if the diode voltage drop is ignored. After the low-side MOSFET turns off, the high-side MOSFET is turned on by

closing an internal switch between BOOT and UGATE. This provides the necessary gate-to-source voltage to turn

(EQ. 17)

Ksh

Vsh



--------------

(EQ. 18)

Rsh

5RFBO1



VOUT



-----------------------------

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