FN8942 Rev.3.0

Page 13 of 25

Jul 30, 2021

ISL70321SEH, ISL73321SEH

3. Typical Performance Curves

Figure 18. DELAY and PGOOD Timer Linearity

Figure 19. Minimum KILL Time

Figure 20. DONE, KILL Threshold Voltage

Figure 21. VDD Rising to VCC5, VREF and EN1 Transition

Figure 22. VDD Falling to VREF EN4 VCC5 Transitions

Figure 23. UP to EN1 Through EN4 Transitions,

10k tDLY Resistor (2ms)

Unless otherwise noted, VDD = 12V; ENx, DONE, KILL are pulled up to VCC5 with a 10k resistor; TDLY and PGTMR resistors are 10k;

VREF and VCC5 are bypassed to GND with a 220nF, and a 470nF capacitor, respectively; TA = +25°C (Continued)

0

5

10

15

20

25

30

35

40

45

10

30

50

70

90

DLYTMR

PGTMR

TIMER RESISTOR (kΩ)

0.0

0.2

0.4

0.6

0.8

1.0

1.2

-55

25

125

tKON 3V

tKON 13V

TEMPERATURE (°C)

0.94

0.95

0.96

0.97

0.98

0.99

1.00

1.01

1.02

1.03

1.04

1.05

-55

25

125

VIH_DONE

VIL_DONE

VIH_KILL

VIL_KILL

TEMPERATURE (°C)

VCC5/UP/INIT

EN1

VDD

VREF

VERT: 1V/DIV

HORZ: 5ms/DIV

VDD

VCC5

EN4

VERT: 1V/DIV

HORZ: 20ms/DIV

VREF

VERT: 2V/DIV

HORZ: 1ms/DIV

UP

EN1

EN2

EN3

EN4