ISL70001ASEHVFE datasheet(21/28 Pages) RENESAS

21 / 28 page

ISL70001ASEH

FN8365 Rev.3.03

Page 21 of 27

Sep 16, 2022

PCB Component Placement

Components should be placed as close as possible to the IC to

minimize stray inductance and resistance. Prioritize the

placement of bypass capacitors on the pins of the IC in the order

shown: REF, SS, AVDD, DVDD, PVINx (high frequency capacitors),

EN, PGOOD, PVINx (bulk capacitors).

Locate the output voltage resistive divider as close as possible to

the FB pin of the IC. The top leg of the divider should connect

directly to the POL (Point of Load), and the bottom leg of the

divider should connect directly to AGND. The junction of the

resistive divider should connect directly to the FB pin.

Locate a Schottky clamp diode as close as possible to the LXx

and PGNDx pins of the IC. A small series R-C snubber connected

from the LXx pins to the PGNDx pins may be used to damp high

frequency ringing on the LXx pins, if desired, see Figure 29.

PCB Layout

Use a small island of copper to connect the LXx pins of the IC to

the output inductor on Layers 1 and 4. To minimize capacitive

coupling to the power and ground planes, void the copper on

Layers 2 and 3 adjacent to the island. Place most of the island of

Layer 4 to minimize the amount of copper that must be voided

from the ground plane (Layer 2).

Keep all other signal traces as short as possible.

For an example layout, see AN1842.

Thermal Management for Ceramic Package

For optimum thermal performance, place a pattern of vias and a

thermal land on the top layer of the PCB directly underneath the

IC. Connect the vias to the plane which serves as a heatsink. To

ensure good thermal contact, thermal interface material such as

a Sil-Pad or thermally conductive epoxy should be used to fill the

gap between the vias and the bottom of the ceramic package.

Lead Strain Relief

The package leads protrude from the bottom of the package and

the leads need forming to provide strain relief. On the ceramic

bottom package R48.A, the Sil-pad or epoxy maybe be used to fill

the gap left between the PCB board and the bottom of the

package when lead forming is completed. On the heatsink option

of the package, R48.B, the lead forming should be made so that

the bottom of the heatsink and the formed leads are flush.

Heatsink Mounting Guidelines

The R48.B package option has a heatsink mounted on the

underside of the package. The following JESD51-5 guidelines

may be used to mount the package:

1. Place a thermal land on the PCB under the heatsink.

2. The land should be approximately the same size as to 1mm

larger than the 9x9mm heatsink.

3. Place an array of thermal vias below the thermal land.

- Via array size: ~8x8 = 64 thermal vias

- Via diameter: ~0.3mm drill diameter with plated copper on

the inside of each via.

- Via pitch: ~1.2mm.

- Vias should drop to and contact as much buried metal area

as feasible to provide the best thermal relief.

Heatsink Electrical Potential

The heatsink is electrically isolated and unbiased. The heatsink

may be electrically connected to any potential which offers the

best thermal relief through conductive mounting materials

(conductive epoxy, solder, etc) or may be left unbiased through

the use of electrically non-conductive mounting materials

(non-conductive epoxy, Sil-pad, kapton film, etc.).

FIGURE 29. SCHOTTKY DIODE AND R-C SNUBBER

COUT

LOUT

VOUT

LXx

VREF

ERROR

AMPLIFIER

REF

CREF

PGNDx

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