ISL70001ASEH

FN8365 Rev.3.03

Page 4 of 27

Sep 16, 2022

Pin Descriptions

PIN NUMBER

PIN NAME

ESD

CIRCUIT

DESCRIPTION

1, 2, 27, 28, 29,

30, 37, 38, 39, 40,

47, 48

PGNDx

-

These pins are the power grounds associated with the corresponding internal power blocks. Connect these

pins directly to the ground plane. These pins should also connect to the negative terminals of the input

and output capacitors. Locate the input and output capacitors as close as possible to the IC.

3, 26, 31, 36, 41,

46

LXx

-

These pins are the outputs of the corresponding internal power blocks and should be connected to the

output filter inductor. Internally, these pins are connected to the synchronous MOSFET power switches. To

minimize voltage undershoot, it is recommended that a Schottky diode be connected from these pins to

PGNDx. The Schottky diode should be located as close as possible to the IC.

4, 5, 24, 25, 32,

33, 34, 35, 42, 43,

44, 45

PVINx

4

These pins are the power supply inputs to the corresponding internal power blocks. These pins must be

connected to a common power supply rail, which must fall in the range of 3V to 5.5V. Bypass these pins

directly to PGNDx with ceramic capacitors located as close as possible to the IC.

6

SYNC

2

This pin is the synchronization I/O for the IC. When configured as an output (Master Mode), this pin drives

the SYNC input of another ISL70001ASEH. When configured as an input (Slave Mode), this pin accepts the

SYNC output from another ISL70001ASEH or an external clock. Synchronization of the slave unit is 180°

out-of-phase with respect to the master unit. If synchronizing to an external clock, the clock must be SEE

hardened and the frequency must be within the range of 1MHz ±20%.

7

M/S

2

This pin is the Master/Slave input for selecting the direction of the bidirectional SYNC pin. For SYNC =

Output (Master Mode), connect this pin to DVDD. For SYNC = Input (Slave Mode), connect this pin to DGND.

8

ZAP

2

This pin is a trim input and is used to adjust various internal circuitry. Connect this pin to DGND.

9

TDI

2

This pin is the test data input of the internal BIT circuitry. Connect this pin to DGND.

10

TDO

2

This pin is the test data output of the internal BIT circuitry. Connect this pin to DGND.

11

PGOOD

5

This pin is the power-good output. This pin is an open drain logic output that is pulled to DGND when the

output voltage is outside a ±11% typical regulation window. This pin can be pulled up to any voltage from

0V to 5.5V, independent of the supply voltage. A nominal 1kΩ to 10kΩ pull-up resistor is recommended.

Bypass this pin to DGND with a 10nF ceramic capacitor to mitigate SEE.

12

SS

2

This pin is the soft-start input. Connect a ceramic capacitor from this pin to DGND to set the soft-start

output ramp time in accordance with Equation 1:

where:

tSS = Soft-start output ramp time

CSS = Soft-start capacitor

VREF = Reference voltage (0.6V typical)

ISS = Soft-start charging current (23µA typical)

Soft-start time is adjustable from approximately 2ms to 200ms.

The range of the soft-start capacitor should be 82nF to 8.2µF, inclusive.

13, 14

DVDD

3

These pins are the bias supply inputs to the internal digital control circuitry. Connect these pins together

at the IC and locally filter them to DGND using a 1Ω resistor and a 1µF ceramic capacitor. Locate both filter

components as close as possible to the IC.

15, 16

DGND

3

These pins are the digital ground associated with the internal digital control circuitry. Connect these pins

directly to the ground plane.

17, 18

AGND

3

These pins are the analog ground associated with the internal analog control circuitry. Connect these pins

directly to the ground plane.

19

AVDD

3

This pin is the bias supply input to the internal analog control circuitry. Locally filter this pin to AGND using

a 1Ω resistor and a 1µF ceramic capacitor. Locate both filter components as close as possible to the IC.

20

REF

1

This pin is the internal reference voltage output. Bypass this pin to AGND with a 220nF ceramic capacitor

located as close as possible to the IC. The bypass capacitor is needed to mitigate SEE. No current (sourcing

or sinking) is available from this pin.

tSS

CSS VREF



ISS



=

(EQ. 1)