ISL6421

FN9130 Rev 1.00

Page 9 of 11

Jul 2004

Received Data (I2C Bus Read Mode)

The ISL6421 can provide to the master a copy of the System

Register information via the I2C bus in read mode. The read

mode is Master activated by sending the chip address with

R/W bit set to 1. At the following Master generated clock bits,

the ISL6421 issues a byte on the SDA data bus line (MSB

transmitted first).

At the ninth clock bit the MCU master can:

• Acknowledge the reception, starting in this way the

transmission of another byte from the ISL6421.

• Not acknowledge, stopping the read mode communication.

While the whole register is read back by the microprocessor,

only the two read-only bits, OLF and OTF, convey diagnostic

information about the ISL6421.

Power–On I2C Interface Reset

The I2C interface built into the ISL6421 is automatically reset

at power-on. The I2C interface block will receive a Power OK

logic signal from the UVLO circuit. This signal will go HIGH

when chip power is OK. As long as this signal is LOW, the

interface will not respond to any I2C commands and the

system register SR is initialized to all zeros, thus keeping the

power blocks disabled.

Once Vcc rises above the UVLO level, the POWER OK signal

given to the I2C interface block will be HIGH, the I2C interface

becomes operative and the SR can be configured by the main

microprocessor. About 400mV of hysteresis is provided in the

UVLO threshold to avoid false triggering of the Power-On reset

circuit.

(I2C comes up with EN = 0, EN goes HIGH at the same time as

(or later than) all other I2C data for the PWM becomes valid).

TABLE 5. SYSTEM REGISTER (SR1 AND SR2) CONFIGURATION

SR

DCL

ISEL1

ENT1

LLC1

VSEL1

EN1

OLF1

FUNCTION

0

1

0

0

1

SR1 is selected

0

1

0

0

1

Vout1 = 13V, Vboost1 = 13V + Vdrop

0

1

0

1

1

Vout1 = 18V, Vboost1 = 18V + Vdrop

0

1

1

0

1

Vout1 = 14V, Vboost1 = 14V + Vdrop

0

1

1

1

1

Vout1 = 19V, Vboost1 = 19V + Vdrop

0

1

0

1

22kHz tone is controlled by the DSQIN pin

0

1

1

1

22kHz tone is ON, the DSQIN input is disabled

0

1

1

1

Dynamic current limit NOT selected

0

0

1

1

Dynamic current limit selected

0

X

1

X

X

X

0

PWM and Linear for channel 1 disabled

SR

----

EN2

OTF

-

FUNCTION

1

X

X

X

X

0

X

X

SR2 is selected; to read OTF flag.

TABLE 6. READING SYSTEM REGISTERS

DCL ISEL ENT LLC VSEL EN OTF OLF

FUNCTION

These bits are read as they were

after the last write operation.

0

Tj <= 130°C, Normal

operation

1

Tj > 150°C, Power

blocks disabled

0

Iout < Imax, Normal

operation

1

Iout > Imax, Overload

protection triggered