ISL6421

FN9130 Rev 1.00

Page 6 of 11

Jul 2004

Functional Description

The ISL6421 single output voltage regulator makes an ideal

choice for advanced satellite set-top box and personal video

recorder applications. Both supply and control voltage outputs

for a low noise block (LNB) are available simultaneously in any

output configuration. The device utilizes a built-in DC/DC step-

converter that, from a single supply source ranging from 8V to

14V, generates the voltage that enables the linear post-

regulator to work with a minimum of dissipated power. An

under voltage lockout circuit disables the circuit when VCC

drops below a fixed threshold (7.5V typ).

DiSEqC Encoding

The internal oscillator is factory-trimmed to provide a tone of

22kHz in accordance with DISeqC standards. No further

adjustment is required. The 22kHz oscillator can be controlled

either by the I2C interface (ENT bit) or by a dedicated pin

(DSQIN) that allows immediate DiSEqC data encoding for the

LNB. All the functions of this IC are controlled via the I2C bus

by writing to the system registers (SR). The same registers can

be read back, and two bits will report the diagnostic status. The

internal oscillator operates the converters at ten times the tone

frequency. The device offers full I2C compatible functionality,

3.3V or 5V, and up to 400kHz operation.

If the Tone Enable (ENT) bit is set LOW through I2C, then the

DSQIN terminal activates the internal tone signal, modulating

the dc output with a 0.3V, 22kHz, symmetrical waveform. The

presence of this signal usually gives the LNB information about

the band to be received.

Burst coding of the 22kHz tone can be accomplished due to

the fast response of the DSQIN input and rapid tone response.

This allows implementation of the DiSEqC (EUTELSAT)

protocols.

When the ENT bit is set HIGH, a continuous 22kHz tone is

generated regardless of the DSQIN pin logic status. The ENT

bit must be set LOW when the DSQIN pin is used for DiSEqC

encoding.

Linear Regulator

The output linear regulator will sink and source current. This

feature allows full modulation capability into capacitive loads

as high as 0.25

F. In order to minimize the power dissipation,

the output voltage of the internal step-up converter is adjusted

to allow the linear regulator to work at minimum dropout.

When the device is put in the shutdown mode (EN = LOW),

the PWM power block is disabled. When the regulator block is

active (EN = HIGH), the output can be logic controlled to be

13V or 18V (typical) by means of the VSEL bit (Voltage Select)

for remote controlling of non-DiSEqC LNBs. Additionally, it is

possible to increment by 1V (typical) the selected voltage value

to compensate for the excess voltage drop along the coaxial

cable (LLC bit HIGH).

Output Timing

Functional Pin Description

SYMBOL

FUNCTION

SDA

Bidirectional data from/to I2C bus.

SCL

Clock from I2C bus.

VSW

Input of the linear post-regulator.

PGND

Dedicated ground for the output gate driver of the PWM.

CS

Current sense input; connect Rsc at this pin for desired over current value for the PWM.

SGND

Small signal ground for the IC.

AGND

Analog ground for the IC.

TCAP

Capacitor for setting rise and fall time of the output of the LNB. Use a capacitor value of 1µF or higher.

BYPASS

Bypass capacitor for internal 5V.

DSQIN

When HIGH this pin enables the internal 22kHz modulation for the LNB, Use this pin for tone enable function for

the LNB.

VCC

Main power supply to the chip.

GATE

This is the device output of the PWM. This high current driver output is capable of driving the gate of a power FET.

This output is actively held low when Vcc is below the UVLO threshold.

VOUT

Output voltage for the LNB.

ADDR

Address pin to select two different addresses per voltage level at this pin.

COMP

Error amp output used for compensation.

FB

Feedback pin for the PWM.

CPVOUT, CPSWIN, CPSWOUT Charge pump connections.

SEL18V

When connected HIGH, this pin will change the output of the PWM to 18V.