M66596 datasheet(28/133 Pages) RENESAS

28 / 133 page

M66596FP/WG

rev .1.00

2006.3.14

page 26 of 127

2.6 FIFO ports

The transmission and reception buffer memory of the controller uses the FIFO. The FIFO port registers should be

used to access the buffer memory. There are three FIFO ports: the CFIFO port, D0FIFO port, and D1FIFO port.

Each FIFO port is configured of a port register that handles reading of data from the buffer memory and writing of

data to the memory, a selection register used to select the pipe assigned to the FIFO port, a control register, and

registers used specifically for port functions (an SIE register used exclusively for the CFIFO port, and a transaction

counter register used exclusively for the DxFIFO port).

The Notes noted below apply to each of the FIFO ports.

1. The DCP buffer memory can only be accessed through the CFIFO port.

2. Accessing the buffer memory using DMA transfer can be done only through the DxFIFO port.

3. Accessing the DxFIFO port using the CPU has to be done in conjunction with the functions and restrictions of

the DxFIFO port.(Using the transaction counter, etc.)

4. When using functions specific to the FIFO port, the selected pipe cannot be changed.

(Using the transaction counter, signal input/output through DMA-related pins, etc.)

5. Registers corresponding to a FIFO port never affect other FIFO ports.

6. The same pipe should not be assigned to two or more separate FIFO ports.

7. There are two sorts of buffer memory states; when the access right is on the CPU side and it is on the SIE

side. When the buffer memory access right is on the SIE side, the memory cannot be properly accessed from

the CPU.

8. The pipe configuration,i.e. PIPECFG, PIPEBUF, PIPEMAXP, PIPEPERI, PIPE1CTR registers of the pipe

selected by the CURPIPE bit should not be changed.

CFIFO port register [CFIFO]

<Address: 10H>

D0FIFO port register [D0FIFO]

<Address: 14H>

D1FIFO port register [D1FIFO]

<Address: 18H>

FIFOPORT

Bit

Name

Function

S/W

H/W

Note

15-0 FIFOPORT

FIFO port

This handles reading of received data from the

buffer memory, or writing of the sent data to the

buffer memory.

R/W

3.4

*1)

<<Note>>

*1) Only the CFIFO port can be used for DCP access of the buffer memory.

Accessing the buffer memory using DMA transfers can only be done through the D0FIFO and D1FIFO ports.

M66596 датащи(PDF) 28 Page - Renesas Technology Corp

M66596 датащи(HTML) 28 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL