January 28, 2014

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IDTP9167

Advanced Datasheet

Power input capacitor – CPVIN

CPVIN is the power input bypass capacitor. As with any switching regulator, this capacitor can supply high transient currents.

The ripple current and ripple voltage can be calculated for the appropriate capacitor using the following approximate equation:

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The voltage ripple across the input capacitor is given by:

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For typical application as described in the EC table, assuming maximum load current of 5.5A, the ripple current through the

capacitor equates to IRMS = 1.95A. When the recommended 2 x 10µF PVIN capacitor is used, the voltage ripple is calculated

to be 22mVPP assuming effective capacitor ESR of 10mΩ. This calculation excludes the effect of series inductance in the

capacitor and the PCB trace leading to it. In actual application, the PVIN voltage spikes caused by this inductance way exceed

the calculated ripple voltage. Therefore, it is recommended that two 10µF capacitors be used instead of a single 22µF.

Additionally, it is recommended that 25V capacitors be used for reliability.

Output capacitor – COUT

The output capacitor temporarily supplies the transient load current as well as provides regulator stability. For stability, the

minimum COUT should be around 100uF per phase, and this should provide reasonable load step response. This value can be

increased to reduce the voltage droop due to load transients but with diminishing effect. The capacitance may be provided

from the load device’s supply bypass capacitor bank, depending upon a few considerations. In general, for regulator stability,

the feedback should be taken across the output capacitor COUT. For most systems, the host PMIC’s Buck regulator feedback

and ground-sense signals will be connected at the load device’s power supply pins and ground connections points

respectively, where usually the supply capacitor bank is also placed. As long as there is at least 94µF per DPU of total

capacitance in the bank, the local COUT at each DPU may be removed. In the case of a distributed power system where

individual DPUs are widely separated on the PCB or far away from the load device, it is recommended to have an additional

10µF ceramic capacitor placed locally at the VOUT side of the inductor connection of each DPU. This local capacitor will absorb

some of the inductor ripple current, reducing EMI effects in the PCB trace connecting VOUT to the load device.

VPG bypass capacitor – CVPG

This is the decoupling capacitor for the internal 5V VSYS-tracking high-side LDO which supplies the high-side switch driving

circuitry, and is connected between the PVIN and VPG pins. A 10V 1µF ceramic capacitor should be used. The voltage

dependency of the capacitor, which can vary with case size, should be such that the de-rated capacitance should be at least

0.8µF when 5V is across it.

VSYS bypass capacitor – CVSYS

This is the input bypass capacitor for the 5V VSYS supply input which powers the low-side switch driving circuitry as well as all

biasing and control circuitry in the device. It is connected between the VSYS and PGND pins. A 10V 4.7µF ceramic capacitor

is recommended.