DATA SHEET

ICS853S024AY REVISION A JULY 20, 2011

1

©2011 Integrated Device Technology, Inc.

Low Skew, 1-to-24, Differential-to-3.3V, 2.5V

LVPECL Fanout Buffer

ICS853S024

General Description

The ICS853S024 is a low skew, 1-to-24 Differential-to-3.3V, 2.5V

LVPECL Fanout Buffer. The PCLK, nPCLK pair can accept most

standard differential input levels. The ICS853S024 is characterized

to operate from either a 3.3V or a 2.5V power supply. Guaranteed

output skew characteristics make the ICS853S024 ideal for those

clock distribution applications demanding well defined performance

and repeatability.

Features

• Twenty four LVPECL outputs.

• One differential clock input pair

• Differential input clock (PCLK, nPCLK) can accept the following

signaling levels: LVDS, LVPECL, CML

• Maximum output frequency: 2GHz

• Translates any single ended input signal to 3.3V, 2.5V LVPECL

levels with resistor bias on nPCLK input

• Output skew: 125ps (maximum)

• Rise and Fall Time: 180ps (typical)

• Additive phase jitter, RMS: 0.15ps (typical) @ 156.25MHz

• Full 3.3V or 2.5V supply voltage

• 0°C to 70°C ambient operating temperature

• Available in lead-free (RoHS 6) package

Q[0:23]

nQ[0:23]

PCLK

nPCLK

Pulldown

Pullup/Pulldown

24

24

Block Diagram

Pin Assignment

VCC

VEE

Q0

Q1

nQ1

Q2

nQ2

nQ0

VCC

nQ3

Q3

Q4

nQ4

Q5

nQ5

VEE

nQ17

Q17

nQ16

PCLK

Q16

nPCLK

nQ15

Q15

VCC

nQ14

Q14

nQ13

Q13

nQ12

Q12

VCC

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

ICS853S024

64-Lead TQFP, EPad

10mm x 10mm x 1mm

package body

Y Package

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