ICS853S024AY REVISION A JULY 20, 2011

9

©2011 Integrated Device Technology, Inc.

ICS853S024 Data Sheet

LOW SKEW, 1-TO-24, DIFFERENTIAL-TO-3.3V, 2.5V LVPECL FANOUT BUFFER

3.3V LVPECL Clock Input Interface

The PCLK /nPCLK accepts LVPECL, LVDS, CML and other

differential signals. Both VSWING and VOH must meet the VPP and

VCMR input requirements. Figures 2A to 2E show interface examples

for the PCLK/ nPCLK input driven by the most common driver types.

The input interfaces suggested here are examples only. If the driver

is from another vendor, use their termination recommendation.

Please consult with the vendor of the driver component to confirm the

driver termination requirements.

Figure 2A. PCLK/nPCLK Input Driven by a CML Driver

Figure 2C. PCLK/nPCLK Input Driven by a

3.3V LVPECL Driver

Figure 2E. PCLK/nPCLK Input Driven by a

3.3V LVDS Driver

Figure 2B. PCLK/nPCLK Input Driven by a

Built-In Pullup CML Driver

Figure 2D. PCLK/nPCLK Input Driven by a

3.3V LVPECL Driver with AC Couple

PCLK

nPCLK

LVPECL

Input

CML

3.3V

Zo = 50

Ω

Zo = 50

Ω

3.3V

3.3V

R1

50

Ω

R2

50

Ω

R3

125

Ω

R4

125

Ω

R1

84

Ω

R2

84

Ω

3.3V

Zo = 50

Ω

Zo = 50

Ω

PCLK

nPCLK

3.3V

3.3V

LVPECL

LVPECL

Input

3.3V

R1

100

Ω

LVDS

PCLK

nPCLK

3.3V

LVPECL

Input

Zo = 50

Ω

Zo = 50

Ω

PCLK

nPCLK

3.3V

LVPECL

Input

3.3V

Zo = 50

Ω

Zo = 50

Ω

R1

100

Ω

CML Built-In Pullup

R3

84

R4

84

R1

125

R2

125

R5

100 - 200

R6

100 - 200

PCLK

nPCLK

3.3V LVPECL

3.3V

Zo = 50

Ω

Zo = 50

Ω

3.3V

3.3V

LVPECL

Input

C1

C2