ICS844256DGI REVISION A AUGUST5, 2010

6

©2010 Integrated Device Technology, Inc.

ICS844256DI Data Sheet

FEMTOCLOCK® CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER

AC Electrical Characteristics

Table 6A. AC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = -40°C to 85°C

NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is

mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium

has been reached under these conditions.

NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential

cross points.

NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.

NOTE 3: Refer to the Phase Noise Plot.

Table 6B. AC Characteristics, VDD = 3.3V ± 5%, VDDO = 2.5V ± 5%, TA = -40°C to 85°C

NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is

mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium

has been reached under these conditions.

NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential

cross points.

NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.

NOTE 3: Refer to the Phase Noise Plot.

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

fOUT

Output Frequency

62.5

625

MHz

tsk(o)

Output Skew; NOTE 1, 2

65

ps

tjit(Ø)

RMS Phase Jitter (Random);

NOTE 3

125MHz (1.875MHz – 20MHz)

0.43

ps

tR / tF

Output Rise/Fall Time

20% to 80%

200

565

ps

odc

Output Duty Cycle

≤ 312.5MHz

47

53

%

> 312.5MHz

45

55

%

tLOCK

PLL Lock Time

25

ms

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

fOUT

Output Frequency

62.5

625

MHz

tsk(o)

Output Skew; NOTE 1, 2

60

ps

tjit(Ø)

RMS Phase Jitter (Random);

NOTE 3

125MHz (1.875MHz – 20MHz)

0.43

ps

tR / tF

Output Rise/Fall Time

20% to 80%

200

615

ps

odc

Output Duty Cycle

≤ 312.5MHz

47

53

%

> 312.5MHz

44

56

%

tLOCK

PLL Lock Time

25

ms