HIP6020A

FN4735 Rev 2.00

Page 11 of 16

September 2001

PWM1 Controller Feedback Compensation

Both PWM controllers use voltage-mode control for output

regulation. This section highlights the design consideration for

a voltage-mode controller requiring external compensation.

Apply these methods and considerations only to the

synchronous PWM controller. The considerations for the

standard PWM controller are presented separately.

Figure 11 highlights the voltage-mode control loop for a

synchronous-rectified buck converter. The output voltage (VOUT)

is regulated to the Reference voltage level. The reference voltage

level is the DAC output voltage (DACOUT) for PWM1. The error

amplifier output (VE/A) is compared with the oscillator (OSC)

triangular wave to provide a pulse-width modulated wave with an

amplitude of VIN at the PHASE node. The PWM wave is

smoothed by the output filter (LO and CO).

The modulator transfer function is the small-signal transfer

function of VOUT/VE/A. This function is dominated by a DC Gain,

given by VIN/VOSC, and shaped by the output filter, with a

double pole break frequency at FLC and a zero at FESR.

Modulator Break Frequency Equations

The compensation network consists of the error amplifier (internal

to the HIP6020A) and the impedance networks ZIN and ZFB. The

goal of the compensation network is to provide a closed loop

transfer function with high 0dB crossing frequency (f0dB) and

adequate phase margin. Phase margin is the difference between

the closed loop phase at f0dB and 180degrees The equations

below relate the compensation network’s poles, zeros and gain to

the components (R1, R2, R3, C1, C2, and C3) in Figure 8. Use

these guidelines for locating the poles and zeros of the

compensation network:

1. Pick Gain (R2/R1) for desired converter bandwidth

2. Place 1ST Zero Below Filter’s Double Pole (~75% FLC)

3. Place 2ND Zero at Filter’s Double Pole

4. Place 1ST Pole at the ESR Zero

5. Place 2ND Pole at Half the Switching Frequency

6. Check Gain against Error Amplifier’s Open-Loop Gain

7. Estimate Phase Margin - Repeat if Necessary

Compensation Break Frequency Equations

Figure 9 shows an asymptotic plot of the DC-DC converter’s gain

vs. frequency. The actual Modulator Gain has a high gain peak

dependent on the quality factor (Q) of the output filter, which is not

shown in Figure 9. Using the above guidelines should yield a

Compensation Gain similar to the curve plotted. The open loop

error amplifier gain bounds the compensation gain. Check the

compensation gain at FP2 with the capabilities of the error

FIGURE 7. PRINTED CIRCUIT BOARD POWER PLANES AND

ISLANDS

VOUT1

Q1

Q2

Q3

Q4

CSS

+12V

CVCC

VIA CONNECTION TO GROUND PLANE

ISLAND ON POWER PLANE LAYER

ISLAND ON CIRCUIT PLANE LAYER

LOUT1

COUT1

CR1

HIP6020A

CIN

COUT2

VOUT2

VOUT3

+5VIN

SS

PGND

LGATE1

UGATE1

PHASE1

DRIVE3

PHASE2

KEY

LOUT2

GND

VCC

UGATE2

OCSET1

OCSET2

ROCSET1

ROCSET2

COCSET1

COCSET2

VOUT4

DRIVE4

+3.3VIN

LIN

CR2

Q5

COUT3

COUT4

FLC

1

2



LO CO





----------------------------------------

=

FESR

1

2

 ESR CO





-----------------------------------------

=

FIGURE 8. VOLTAGE-MODE BUCK CONVERTER

COMPENSATION DESIGN

VOUT

OSC

REFERENCE

LO

CO

ESR

VIN

VOSC

ERROR

AMP

PWM

DRIVER

(PARASITIC)

ZFB

+

-

DACOUT

R1

R3

R2

C3

C2

C1

COMP

VOUT

FB

ZFB

HIP6020A

ZIN

COMP

DRIVER

DETAILED COMPENSATION COMPONENTS

PHASE

VE/A

+

-

+

-

ZIN

FZ1

1

2

 R

 2C1



-----------------------------------

=

FZ2

1

2



R1 R3

+

 C3





-------------------------------------------------------

=

FP1

1

2

 R2

C1 C2



C1 C2

+

----------------------









-------------------------------------------------------

=

FP2

1

2

 R

 3C3



-----------------------------------

=