HIP6020A

FN4735 Rev 2.00

Page 6 of 16

September 2001

Functional Pin Descriptions

VCC (Pin 28)

Provide a 12V bias supply for the IC to this pin. This pin also

provides the gate bias charge for all the MOSFETs controlled

by the IC. The voltage at this pin is monitored for Power-On

Reset (POR) purposes.

GND (Pin 17)

Signal ground for the IC. All voltage levels are measured with

respect to this pin.

PGND (Pin 24)

This is the power ground connection. Tie the synchronous

PWM converter’s lower MOSFET source to this pin.

VAUX (Pin 16)

The +3.3V input voltage at this pin is monitored for power-on

reset (POR) purposes. Connected to +5V input, this pin

provides boost current for the two linear regulator output drives

in the event bipolar NPN transistors (instead of N-Channel

MOSFETs) are employed as pass elements.

SS (Pin 12)

Connect a capacitor from this pin to ground. This capacitor,

along with an internal 28

A current source, sets the soft-start

interval of the converter.

FAULT / RT (Pin 13)

This pin provides oscillator switching frequency adjustment. By

placing a resistor (RT) from this pin to GND, the nominal

200kHz switching frequency is increased according to the

following equation:

Conversely, connecting a pull-up resistor (RT) from this pin to

VCC reduces the switching frequency according to the

following equation:

Nominally, the voltage at this pin is 1.26V. In the event of an

over-voltage or over-current condition, this pin is internally

pulled to VCC.

PGOOD (Pin 8)

PGOOD is an open collector output used to indicate the status

of the output voltages. This pin is pulled low when the

synchronous regulator output is not within

10%of the

DACOUT reference voltage or when any of the other outputs

are below their under-voltage thresholds.

The PGOOD output is open for ‘11111’ VID code.

VID0, VID1, VID2, VID3, VID4 (Pins 7, 6, 5, 4 and 3)

VID0-4 are the TTL-compatible input pins to the 5-bit DAC. The

logic states of these five pins program the internal voltage

reference (DACOUT). The level of DACOUT sets the

microprocessor core converter output voltage, as well as the

corresponding PGOOD and OVP thresholds.

OCSET1, OCSET2 (Pins 23 and 9)

Connect a resistor (ROCSET) from this pin to the drain of the

respective upper MOSFET. ROCSET, an internal 200A

current source (IOCSET), and the upper MOSFET’s on-

resistance (rDS(ON)) set the converter over-current (OC) trip

point according to the following equation:

An over-current trip cycles the soft-start function.

The voltage at OCSET1 pin is monitored for power-on reset

(POR) purposes.

PHASE1, PHASE2 (Pins 26 and 2)

Connect the PHASE pins to the respective PWM converter’s

upper MOSFET source. These pins represent the gate drive

return current path and are used to monitor the voltage drop

across the upper MOSFETs for over-current protection.

UGATE1, UGATE2 (Pins 27 and 1)

Connect UGATE pins to the respective PWM converter’s upper

MOSFET gate. These pins provide the gate drive for the upper

MOSFETs. For SELECT high, UGATE2 is turned on

continuously to provide a DC current flow path to VOUT2.

LGATE1 (Pin 25)

Connect LGATE1 to the synchronous PWM converter’s lower

MOSFET gate. This pin provides the gate drive for the lower

MOSFET.

COMP1 and FB1 (Pins 20, and 21)

COMP1 and FB1 are the available external pins of the

synchronous PWM regulator error amplifier. The FB1 pin is the

inverting input of the error amplifier. Similarly, the COMP1 pin

is the error amplifier output. These pins are used to

compensate the voltage-mode control feedback loop of the

synchronous PWM converter.

VSEN1 (Pin 22)

This pin is connected to the synchronous PWM converters’

output voltage. The PGOOD and OVP comparator circuits use

this signal to report output voltage status and for over- voltage

protection.

VSEN2 (Pin 10)

Connect this pin to the output of the standard buck PWM

regulator. The voltage at this pin is regulated to 1.5V if the

SELECT pin is low. This pin is also monitored by the PGOOD

comparator circuit.

SELECT (Pin 11)

This pin determines the output voltage of the AGP bus

switching regulator. A low TTL input sets the output voltage to

Fs 200KHz

510

6



RT k



---------------------

+



(RT to GND)

Fs 200KHz

410

7



RT k



---------------------

–



(RT to 12V)

IPEAK

IOCSET ROCSET



rDS ON



----------------------------------------------------

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