RENESAS TECHNICAL UPDATE

TN-SH7-A826A/E

Date: December 27, 2011

Page 2 of 4

* In the following, the portion of net credit ( ) or an underline is a portion with an addition/change.

Rev.

Page

Part

Contents

Revision History: Description of CAN added

-Page of Previous Edition: 26-49

-Description:

Description of the bit 1 (SDST bit) in the CANi Status Register (CiSTR)

(i=0 to 4) corrected

Error: The SDST bit is set to "1" when at least one SENTDATA bit

in the CiMCTLj register is "1" regardless of the value of the

CiMIER register.

Correct: The SDST bit is set to "1" when at least one SENTDATA bit

in the CiMCTLj (j = 32 to 63) register is "1" regardless of the

value of the CiMIER register.

-Page of Previous Edition: 26-49

-Description:

Description of the bit 0 (NDST bit) in the CANi Status Register (CiSTR)

(i=0 to 4) corrected

Error: The NDST bit is set to "1" when at least one NEWDATA bit in

the CiMCTLj register is "1" regardless of the value of the

CiMIER register.

Adds

by

REV.A

Revision

History

- xiii

26.3.14

CANi Status

Register

Correct: The NDST bit is set to "1" when at least one NEWDATA bit

in the CiMCTLj (j = 0 to 63) register is "1" regardless of the

value of the CiMIER register.

Revision History: Description of FlexRay added

-Page of Previous Edition: 32-17

-Description:

Description of the bit 24 (EDB bit) in the FlexRay Error Interrupt

Register (FREIR) corrected

Error: 0: No error detected on channel B RW

Correct: 0: No error detected on channel B

-Page of Previous Edition: 32-18

-Description:

Description of the bit 9 (IIBA bit) in the FlexRay Error Interrupt

Register (FREIR) corrected

Error: 0: No illegal CPU access to Output Buffer occurred

1: Illegal CPU access to Output Buffer occurred

Adds

by

REV.A

Revision

History

- xv

32.5.1

FlexRay Error

Interrupt

Register

Correct: 0: No illegal CPU access to Input Buffer occurred

1: Illegal CPU access to Input Buffer occurred

Revision History: Description of Appendix A added

-Page of Previous Edition: A-1

-Description:

Value after reset of the bit 5 (RABD bit) in the CPU Operation Mode

Register (CPUOPM) revised

Error: Value after reset of the RABD bit is "1"

Adds

by

REV.A

Revision

History

- xvi

Appendix A

CPU Operation

Mode Register

Correct: Value after reset of the RABD bit is " 0"

Description of the bit 29 to 24 (PSL5 to PSL0 bit) in the FlexRay CC

Status Vector Register (FRCCSV) corrected

Error: Set to B’000100 when leaving HALT state.

Adds

by

REV.A

32-76

32.7.1

FlexRay CC

Status Vector

Register

Correct: Set to B’000000 when leaving HALT state.