RENESAS TECHNICAL UPDATE

TN-SH7-A826A/E

Date: December 27, 2011

Page 4 of 4

Rev.

Page

Part

Contents

Table 38.29 DRI Timing (When Special Mode is On) : Incorrect

description corrected.

Error:

Item

Symbol

Min.

Max.

Unit

Figures

DIN2 to DIN4 sampling

edge undefined time

before DIN1

initialization level

release (when direct

reset is selected)

tar

8

-

ns

DIN2 to DIN4 sampling

edge undefined time

before DIN1

initialization level

release

tbr

12

-

ns

38.33

to

38.36

Adds

by

REV.C

38-38

Table 38.29

DRI Timing

(When Special

Mode is On)

Correct:

Item

Symbol

Min.

Max.

Unit

Figures

DIN2 to DIN4 sampling

edge undefined time

before DIN1

initialization level

release

tar

8

-

ns

DIN2 to DIN4 sampling

edge undefined time

after DIN1 initialization

level release

tbr

12

-

ns

38.33

to

38.36

Table 38.35 AUDR Module Timing (PVcc=5.0V) : Incorrect description

corrected.

Error:

Item

Symbol

Min.

Max.

Unit

Figures

AUDRD output delay

time before AUDRCLK

td(AUDRCLKH-

AUDRD)

-

35

ns

38.46

Adds

by

REV.A

38-46

Table 38.35

AUDR Module

Timing

(PVcc=5.0V)

Correct:

Item

Symbol

Min.

Max.

Unit

Figures

AUDRD output delay

time after AUDRCLK

td(AUDRCLKH-

AUDRD)

-

35

ns

38.46

Table 38.36 AUDR Module Timing (PVcc=3.3V) : Incorrect description

corrected.

Error:

Item

Symbol

Min.

Max.

Unit

Figures

AUDRD output delay

time before AUDRCLK

td(AUDRCLKH-

AUDRD)

-

40

ns

38.46

Adds

by

REV.A

38-47

Table 38.36

AUDR Module

Timing

(PVcc=3.3V)

Correct:

Item

Symbol

Min.

Max.

Unit

Figures

AUDRD output delay

time after AUDRCLK

td(AUDRCLKH-

AUDRD)

-

40

ns

38.46