Philips Semiconductors Linear Products

Product specification

ADC0820

8-Bit, high-speed,

µP-compatible A/D converter with

track/hold function

August 31, 1994

575

FUNCTIONAL DESCRIPTION

General Operation

The ADC0820 uses two 4-bit flash A/D converters to make an 8-bit

measurement (Block Diagram). Each flash ADC is made up of 15

comparators which compare the unknown input to a reference

ladder to get a 4-bit result. To take a full 8-bit reading, one flash

conversion is done to provide the 4 most significant data bits (via the

MS flash ADC). Driven by the 4 MSBs, an internal DAC recreates an

analog approximation of the input voltage. This analog signal is then

subtracted from the input, and the difference voltage is converted by

a second 4-bit flash ADC (the LS ADC), providing the 4 least

significant bits of the output data word.

The internal DAC is actually a subsection of the MS flash converter.

This is accomplished by using the same resistor ladder for the A/D

as well as for generating the DAC signal. The DAC output is actually

the tap on the resistor ladder which most closely approximates the

analog input. In addition, the “sampled data” comparators used in

the ADC0820 provide the ability to compare the magnitudes of

several analog signals simultaneously, without using input summing

amplifiers. This is especially useful in the LS flash ADC, where the

signal to be converted is an analog difference.

The Sampled-Data Comparator

Each comparator in the ADC0820 consists of a CMOS inverter with

a capacitively-coupled input (Figure 4). Analog switches connect the

two comparator inputs to the input capacitor (C) and also connect

the inverter’s input and output. This device in effect now has one

differential input pair. A comparison requires two cycles, one for

zeroing the comparator, and another for making the comparison.

In the first cycle, one input switch and the inverter’s feedback switch

(Figure 4a) are closed. In this interval, C is charged to the

approximately 1.6V). In the second cycle (Figure 4b), these two

switches are opened and the other (V2) input’s switch is closed. The

input capacitor now subtracts its stored voltage from the second

input and the difference is amplified by the inverter’s open loop gain.

V

S

+ V

C

C

) C

S

The actual circuitry used in the ADC0820 is a simple but important

expansion of the basic comparator described above. By adding a

second capacitor and another set of switches to the input (Figure 5),

the scheme can be expanded to make dual differential comparisons.

In this circuit, the feedback switch and one input switch on each

capacitor (Z switches) are closed in the zeroing cycle. A comparison

is then made by connecting the second input on each capacitor (S

switches) and opening all of the other switches. The change in

voltage at the inverter’s input, as a result of the change in charge on

each input capacitor, will now depend on both input signal

differences.

Architecture

In the ADC0820, 15 comparators are used in the MS and LS 4-bit

flash A/D converters. The MS (most significant) flash ADC also has

one additional comparator to detect input over-range. These two

sets of comparators operate alternately, with one group in its zeroing

cycle while the other is comparing.

• VS’ – VS = (V2 – V1)

• VO’ =

[CV2 – CV1]

• VO’ IS DEPENDENT ON V2–V1

C

C + CS

–A

C + CS

V1

V2

C

VS

CS

VO

a. Zeroing Phase

b. Compare Phase

V1

V2

C

VS

CS

VO

• VO = VS

• V ON C = V1 – VB

• CS = SATRAY INPUT NODE CAPACITOR

• VS = INVERTER INPUT BIAS VOLTAGE

A

A

Figure 4. Sampled Data Comparator

VO =

[C1 (V2 – V1) + C2 (V4–V3)]

=

–A

C1 + C2 + CS

VS

CS

VO

A

C1

C2

S

Z

Z

S

Z

R LADDER (V1)

VIN (V2)

ANALOG GND

(V3)

1/2 LSB (V4)

–A

C1 + C2 + CS

Figure 5. ADC0820 Comparator (From MS Flash ADC)