83C751 datasheet(16/24 Pages) PHILIPS

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Philips Semiconductors

Product specification

83C751/87C751

80C51 8-bit microcontroller family

2K/64 OTP/ROM, I2C, low pin count

1998 May 01

Table 4.

Interaction of TIRUN with SLAVEN, MASTRQ, and MASTER

SLAVEN,

MASTRQ,

MASTER

TIRUN

OPERATING MODE

All 0

The I2C interface is disabled. Timer I is cleared and does not run. This is the state assumed after a reset. If an I2C

application wants to ignore the I2C at certain times, it should write SLAVEN, MASTRQ, and TIRUN all to zero.

All 0

The I2C interface is disabled. Timer I operates as a free-running time base. Use this mode only in non-I2C

applications.

Any or all 1

The I2C interface is enabled. The 3 low-order bits of Timer I run for min-time generation, but the hi-order bits do

not, so that there is no checking for I2C being “hung.” This configuration can be used for very slow I2C operation.

Any or all 1

The I2C interface is enabled. Timer I runs during frames on the I2C, and is cleared by transitions on SCL, and by

Start and Stop conditions. This is the normal state for I2C operation.

Table 5.

CT1, CT0 Values

CT1, CT0

OSC/12 COUNT

fOSC MAX

TIMEOUT PERIOD

16.8MHz

1023 cycles

14.4MHz

1022 cycles

12.0MHz

1021 cycles

9.6MHz

1020 cycles

I2C Register I2STA

READ ONLY

–

IDLE

XDATA

XACTV

MAKSTR

MAKSTP

XSTR

XSTP

MSB

LSB

This register is read only and reflects the internal status of the I2C

hardware. IDLE, XSTR, and XSTP reflect the status of the like

named bits in the I2CON register.

XDATA

The content of the transmitter buffer.

XACTV

Transmitter active.

MAKSTR This bit is high while the hardware is effecting a start

condition.

MAKSTP This bit is high while the hardware is effecting a stop

condition.

XSTR

This bit is active while the hardware is effecting a

repeated start condition.

XSTP

This bit is active while the hardware is effecting a

repeated stop condition.

Interrupts

The interrupt structure is a five-source, one-level interrupt system.

Interrupt sources common to the 80C51 are the external interrupts

(INT0, INT1) and the timer/counter interrupt (ET0). The I2C interrupt

(EI2) and Timer I interrupt (ETI) are the other two interrupt sources.

The interrupt sources are listed below in their order of polling

sequence priority.

Upon interrupt or reset the program counter is loaded with specific

values for the appropriate interrupt service routine in program

memory. These values are:

Program Memory

Event

Address

Priority

Reset

000

Highest

INT0

003

Counter/Timer 0

00B

INT1

013

Timer I

01B

I2C

023

Lowest

The interrupt enable register (IE) is used to individually enable or

disable the five sources. Bit EA in the interrupt enable register can

be used to globally enable or disable all interrupt sources. The

interrupt enable register is described below. All other interrupt details

are based on the 80C51 interrupt architecture.

Interrupt Enable Register

EI2

ETI

EX1

ET0

EX0

Symbol Position

Function

IE.7

Disables all interrupts. If EA = 0, no interrupt

will be acknowledged. If EA = 1, each interrupt

source is individually enabled or disabled by

setting or clearing its enable bit

–

IE.6

Reserved

–

IE.5

Reserved

EI2

IE.4

Enables or disables the I2C interrupt.

If EI2 = 0, the I2C interrupt is disabled

ETI

IE.3

Enables or disables the Timer I overflow

interrupt. If ETI = 0, the Timer I interrupt is

disabled.

EX1

IE.2

Enables or disables external interrupt 1.

If EX1 = 0, external interrupt 1 is disabled.

ET0

IE.1

Enables or disables the Timer 0 overflow

interrupt. If ET0 = 0, theTimer 0 interrupt is

disabled.

EX0

IE.0

Enables or disables external interrupt 0.

If EX0 = 0, external interrupt 0 is disabled.

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